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Prediction router: Yet another low latency on-chip router architecture

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2009 2009 IEEE 15th International Symposium on High Performance Computer Architecture  
Outline: Prediction router for low-latency NoC • Existing low-latency routers -Speculative router -Look-ahead router -Bypassing routerPrediction router -Architecture and the prediction algorithms  ...  Their communication latency is a crucial problem Number of hops increases Low-latency router architecture has been extensively studied Why low-latency router is needed?  ... 
doi:10.1109/hpca.2009.4798274 dblp:conf/hpca/MatsutaniKAY09 fatcat:akcjgd7pvbamreppn2utimx2ka

Benefits and costs of prediction based DVFS for NoCs at router level

Cristinel Ababei, Nicholas Mastronarde
2014 2014 27th IEEE International System-on-Chip Conference (SOCC)  
Power consumption remains one of the most important design objectives for network-on-chip (NoC) based systems. In this paper, we focus on the NoC component of these systems.  ...  The proposed distributed DVFS algorithm uses history based predictors that predict link and buffer utilizations.  ...  We thank Susan Schneider for feedback on an early draft of this presentation.  ... 
doi:10.1109/socc.2014.6948937 dblp:conf/socc/AbabeiM14 fatcat:f7aq4c3srzagrdgqh73jclr6ou

Asynchronous spatial division multiplexing router

Wei Song, Doug Edwards
2011 Microprocessors and microsystems  
Area and latency models are provided to analyse the network performance of all router architectures including wormhole, virtual channel and SDM.  ...  A novel asynchronous SDM router architecture is presented.  ...  The Chain interconnection network [9] was employed in SpiNNaker CMP chips [10] to connect all on-chip processors to a central router. Up to now, SDM has not been implemented asynchronously yet.  ... 
doi:10.1016/j.micpro.2010.08.007 fatcat:kfhc24ph35gpxch7debnjtqsvy

The Implementation of a Low Cost Single-cycle On-chip Router Based on Multiple Virtual Output Queuing

Son Truong Nguyen, Shigeru Oyanagi
2011 IPSJ Online Transactions  
Its architecture significantly impacts on the performance of NoC. In this paper, we propose a low latency router architecture based on virtual output queuing (VOQ).  ...  Network-on-Chip (NoC) is becoming a popular solution for communication on System-on-Chips. A router is a major component of NoC which is responsible for handling the communication.  ...  International Symposium on Networks-on-Chip (NOCS'07 ), pp.153-162 (2007). 13) Matsutani, H., Koibuchi, M., Amano, H. and Yoshinaga, T.: Prediction Router: Yet Another Low Latency On-Chip Router Architecture  ... 
doi:10.2197/ipsjtrans.4.33 fatcat:c4omez67nzhfxilsisef4jdkjy

Adapting router buffers for energy efficiency

Arun Vishwanath, Vijay Sivaraman, Zhi Zhao, Craig Russell, Marina Thottan
2011 Proceedings of the Seventh COnference on emerging Networking EXperiments and Technologies on - CoNEXT '11  
Dynamic adjustment of active router buffer size provides a low-complexity low-risk mechanism of saving energy that is amenable for incremental deployment in networks today.  ...  Our study shows that much of the energy associated with off-chip packet buffers can be eliminated with negligible impact on traffic performance.  ...  It should also be noted that router manufacturers typically use specialised low-latency DRAMs such as Fast Cycle RAM (FCRAM) and Reduced Latency DRAM (RLDRAM), which consume about 40% more power than mass-market  ... 
doi:10.1145/2079296.2079315 dblp:conf/conext/VishwanathSZRT11 fatcat:q22nmaxlrzh4bbnz6danrkd7ny

A High-throughput Router Architecture with On-the-fly Virtual Channel Allocation for On-chip Networks

Son Truong Nguyen, Shigeru Oyanagi
2011 IPSJ Online Transactions  
Designing high throughput and low latency on-chip networks with reasonable area overhead is becoming a major technical challenge.  ...  This paper proposes an architecture of router with on-the-fly virtual channel (VC) allocation for high performance on-chip networks.  ...  This fact indicates the ability of our proposed architecture to provide low cost high performance on-chip networks for practical SoCs.  ... 
doi:10.2197/ipsjtrans.4.84 fatcat:lompy3sjffazthwhlfv26nnef4

Design of a High-Throughput Distributed Shared-Buffer NoC Router

Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh
2010 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip  
Router microarchitecture plays a central role in the performance of an on-chip network (NoC).  ...  In this paper, we propose a new router design that aims to emulate an OBR practically, based on a distributed shared-buffer (DSB) router architecture.  ...  Finally, another key difference is the need for on-chip routers to operate at aggressive clock frequencies.  ... 
doi:10.1109/nocs.2010.17 dblp:conf/nocs/RamanujamSLP10 fatcat:mbpauph7qzgo3gqn4euobkpmeu

Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers

Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Router microarchitecture plays a central role in the performance of networks-on-chip (NoCs).  ...  Compared to a state-of-the-art pipelined IBR, the proposed DSB router achieves up to 19% higher throughput on synthetic traffic and reduces packet latency on average by 61% when running SPLASH-2 benchmarks  ...  Although based on the DSB architecture used in Internet routers, the proposed NoC router architecture faces a number of challenges specific to the on-chip domain.  ... 
doi:10.1109/tcad.2011.2110550 fatcat:zzxrr5tm65aphfevycpjejxc2e

A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] [chapter]

Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
2009 Lecture Notes in Electrical Engineering  
This attribute substantially reduces global wiring length in 3D chips. The work in this paper integrates the increasingly popular idea of packet-based Networks-on-Chip (NoC) into a 3D setting.  ...  and throughput improvements of over 20% on average over the other 3D architectures, while remaining within 5% of the full 3D crossbar performance.  ...  Networks-on-Chip The design of efficient on-chip router architectures has been the main focus of many researchers in the past few years.  ... 
doi:10.1007/978-90-481-3031-3_9 fatcat:cazlh6m3lzbpziigujbagahaum

Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

E. Rijpkema, K. Goossens, A. Rdulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander
2003 IEE Proceedings - Computers and digital Techniques  
For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used.  ...  We combine the GT and BE router architectures in an efficient implementation by sharing resources.  ...  Another example is cache updates which require uncorrupted, lossless, low-latency data transfer, but ordering and guaranteed throughput are less important.  ... 
doi:10.1049/ip-cdt:20030830 fatcat:pdvsfdsh3vg4dnfv4fuxin5cou

Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip [chapter]

E. Rijpkema, K. G. W. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander
2008 Design, Automation, and Test in Europe  
For the communication, scalable and compositional interconnects, such as networks on chip (NoC), must be used.  ...  We combine the GT and BE router architectures in an efficient implementation by sharing resources.  ...  Another example is cache updates which require uncorrupted, lossless, low-latency data transfer, but ordering and guaranteed throughput are less important.  ... 
doi:10.1007/978-1-4020-6488-3_10 fatcat:h6sl7vjenzb2dowx3zfmvnkuoe

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
This attribute substantially reduces global wiring length in 3D chips. The work in this paper integrates the increasingly popular idea of packet-based Networks-on-Chip (NoC) into a 3D setting.  ...  and throughput improvements of over 20% on average over the other 3D architectures, while remaining within 5% of the full 3D crossbar performance.  ...  Networks-on-Chip The design of efficient on-chip router architectures has been the main focus of many researchers in the past few years.  ... 
doi:10.1145/1250662.1250680 dblp:conf/isca/KimNPDXVYD07 fatcat:py7vyhahynd57l4vgif7ni7ete

Multi-Terabyte and multi-Gbps information centric routers

G. Rossini, D. Rossi, M. Garetto, E. Leonardi
2014 IEEE INFOCOM 2014 - IEEE Conference on Computer Communications  
architectures.  ...  One of the main research directions along which the future Internet is evolving can be identified in the paradigmatic shift from a network of hosts toward a network of caches.  ...  Interestingly, [5] also proposes an edge router design where a 1TB SSD cache is indexed by a 10GB DRAM chip.  ... 
doi:10.1109/infocom.2014.6847938 dblp:conf/infocom/RossiniRGL14 fatcat:l3crqelpinhvvhbm5myhdstjfe

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Vijaykrishnan Narayanan, Mazin S. Yousif, Chita R. Das
2007 SIGARCH Computer Architecture News  
This attribute substantially reduces global wiring length in 3D chips. The work in this paper integrates the increasingly popular idea of packet-based Networks-on-Chip (NoC) into a 3D setting.  ...  and throughput improvements of over 20% on average over the other 3D architectures, while remaining within 5% of the full 3D crossbar performance.  ...  Networks-on-Chip The design of efficient on-chip router architectures has been the main focus of many researchers in the past few years.  ... 
doi:10.1145/1273440.1250680 fatcat:yrbacnsotnbmnhuauevauimwsq

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

Evangelia Kasapaki, Jens Sparso, Rasmus Bo Sorensen, Kees Goossens
2013 2013 Euromicro Conference on Digital System Design  
English) Multi-processor architectures using networks-on-chip (NOCs) for communication are becoming the standard approach in the development of embedded systems and general purpose platforms.  ...  Argo uses a novel NI design that supports time-predictability, and asynchronous routers that form a time-elastic network.  ...  The CoMPSOC platform has a scalable tile-based architecture [101] , [102] with composability and predictability properties. Communication in the CoMPSoC platform is based on a network-on-chip.  ... 
doi:10.1109/dsd.2013.40 dblp:conf/dsd/KasapakiSSG13 fatcat:yzvmstcvkvgfnbm5wysn2ipray
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