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PARE
<span title="">2005</span>
<i title="ACM Press">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qcoemsk4lfgznflartfnzb5rhy" style="color: black;">Proceedings of the 2005 international symposium on Low power electronics and design - ISLPED '05</a>
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Compared to the conventional single table design, the new prefetching table consumes 7-11X less power per access. ...
In this paper, we present PARE, a Power-Aware pRefetching Engine that uses a newly designed indexed hardware history table. ...
Although considerable research [16, 3, 13, 14, 5, 11, 9, 10] has been focused on improving the performance of prefetching mechanisms, the impact of prefetching techniques on processor energy efficiency ...
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PARE: a power-aware hardware data prefetching engine
<span title="">2005</span>
<i title="IEEE">
ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.
</i>
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Compared to the conventional single table design, the new prefetching table consumes 7-11X less power per access. ...
In this paper, we present PARE, a Power-Aware pRefetching Engine that uses a newly designed indexed hardware history table. ...
Although considerable research [16, 3, 13, 14, 5, 11, 9, 10] has been focused on improving the performance of prefetching mechanisms, the impact of prefetching techniques on processor energy efficiency ...
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<a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/lpe.2005.195544">doi:10.1109/lpe.2005.195544</a>
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Redesigning a tagless access buffer to require minimal ISA changes
<span title="">2016</span>
<i title="ACM Press">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/h3qjmo5xyfe6fcrh4fogxmkkiq" style="color: black;">Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems - CASES '16</a>
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Energy efficiency is a first-order design goal for nearly all classes of processors, but it is particularly important in mobile and embedded systems. ...
Strided memory references are redirected from the level-one data cache (L1D) to the smaller, more energy-efficient TAB. ...
The signed nine-bit prefetch offset limits the distance between the gtab and the prefetching reference instruction: this is why the prefetch PC field only needs ten bits. ...
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Chameleon
<span title="2010-04-01">2010</span>
<i title="Association for Computing Machinery (ACM)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/jfrn2kjyarhe7npmgvoxdp4cxu" style="color: black;">ACM Transactions on Architecture and Code Optimization (TACO)</a>
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Therefore, no areaand power-hungry router is required. ...
Heterogeneous multicore processors have emerged as an energy-and area-efficient architectural solution to improving performance for domain-specific applications such as those with a plethora of data-level ...
ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, Article 3, Publication date: April 2010.
Chameleon: Virtualizing Idle Cores for Caching and Prefetching ...
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Energy-Efficient Hardware Data Prefetching
<span title="">2011</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a>
</i>
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Index Terms-Compiler analysis, data prefetching, energy efficiency, prefetch filtering, prefetch hardware. ...
These include compiler-assisted and hardware-based energy-aware techniques and a new power-aware prefetch engine that can reduce hardware prefetching related energy consumption by 7-11 . ...
We also use one bit to indicate the prefetching type and two bits for status, as mentioned previously. Finally, each entry also contains the lower 12 bits of the predicted stride/offset value. ...
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Low-power design for embedded processors
<span title="">2001</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a>
</i>
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Minimization of power consumption in portable and batterypowered embedded systems has become an important aspect of processor and system design. ...
A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made ...
EMBEDDED PROCESSOR EXAMPLE Low-power embedded processors fall into several categories. ...
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High-Performance Energy-Efficient Multicore Embedded Computing
<span title="">2012</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ll6bfs5o6bahfinh3u5z2cnyoy" style="color: black;">IEEE Transactions on Parallel and Distributed Systems</a>
</i>
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The increase in on-chip transistor density exacerbates power/thermal issues in embedded systems, which necessitates novel hardware/software power/thermal management techniques to meet the ever-increasing ...
high-performance embedded computing demands in an energy-efficient manner. ...
512 low-power X86 1.66 GHz, 64-bit, Intel Atom cores [64] ). ...
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IBM POWER8 processor core microarchitecture
<span title="">2015</span>
<i title="IBM">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cr766v23pncdhc7hmikak4m7pi" style="color: black;">IBM Journal of Research and Development</a>
</i>
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Going against this industry trend, the POWER8 processor relies on a much improved core and nest microarchitecture to achieve approximately one-and-a-half times the single-thread performance and twice the ...
It is fabricated using the company's 22-nm Silicon on Insulator (SOI) technology with 15 layers of metal, and it has been designed to significantly improve both single-thread performance and single-core ...
Acknowledgments A large number of people worked on the POWER8 processor core microarchitecture described in this paper. ...
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T-CREST: Time-predictable multi-core architecture for embedded systems
<span title="">2015</span>
<i title="Elsevier BV">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/abrqcwwp5bajjj4an3guihtf7u" style="color: black;">Journal of systems architecture</a>
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Standard multi-core processors are optimized for the average case and are hardly analyzable. ...
An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. ...
(real-time), low-power embedded systems. ...
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Overview of the IBM Blue Gene/P project
<span title="">2008</span>
<i title="IBM">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cr766v23pncdhc7hmikak4m7pi" style="color: black;">IBM Journal of Research and Development</a>
</i>
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The Blue Gene/P project has been supported and partially funded by Argonne National Laboratory and the Lawrence Livermore National Laboratory on behalf of the U.S. ...
As depicted in Figure 1 , the BPC chip is a single ASIC with four IBM PowerPC 450 (PPC450)embedded 32-bit processor cores, arranged as an SMP. ...
Processor cores are statically assigned, or bound, to application processes. ...
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Performance Evaluation of Scientific Applications on POWER8
[chapter]
<span title="">2015</span>
<i title="Springer International Publishing">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a>
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With POWER8 a new generation of POWER processors became available. ...
For a set of applications with significantly different performance signatures we explore efficient use of this processor architecture. ...
In June 2014 the most recent generation of POWER processors, namely POWER8, became available in a pre-release program. ...
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A Survey of Machine Learning for Computer Architecture and Systems
[article]
<span title="2021-02-16">2021</span>
<i >
arXiv
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<span class="release-stage" >pre-print</span>
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It has been a long time that computer architecture and systems are optimized to enable efficient execution of machine learning (ML) algorithms or models. ...
For ML-based modelling, we discuss existing studies based on their target level of system, ranging from the circuit level to the architecture/system level. ...
on a target ARM processor. ...
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Architectural and Operating System Support for Virtual Memory
<span title="2017-09-29">2017</span>
<i title="Morgan & Claypool Publishers LLC">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ebvqyf4cvbgd5icaupgsf35vam" style="color: black;">Synthesis Lectures on Computer Architecture</a>
</i>
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On a personal note, we would like to thank Shampa Sanyal for enabling our research endeavors, and we would like to thank our respective families for making this all possible in the first place. ...
Guilherme Cox, Babak Falsafi, Gabriel Loh, Tushar Krishna, Mark Oskin, David Nellans, Binh Pham, Bharath Pichai, Geet Sethi, Jan Vesely, and Zi Yan deserve special mention for making a direct impact on ...
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Measurement of current variations for the estimation of software-related power consumption
<span title="">2003</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ezthgawmfbeczntonmx4gfjvtm" style="color: black;">IEEE Transactions on Instrumentation and Measurement</a>
</i>
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The problem addressed is to measure the variations of the power supply current of digital circuits (and especially of embedded processing circuits) and to calculate from these measurements the energy consumption ...
processor (core) and of the overall processing system as well (consumption of peripheral units). ...
Other costs can be assigned to encompass factors that have substantial impact on the overall power figures. These depend on the micro architectural characteristics of the specific processor. ...
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Architectural support for uniprocessor and multiprocessor active memory systems
<span title="">2004</span>
<i title="Institute of Electrical and Electronics Engineers (IEEE)">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a>
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However, they create coherence problems since the processor is allowed to refer to the same data via more than one address. ...
We leverage and extend the cache coherence protocol so that our techniques work transparently to efficiently support uniprocessor, SMP and DSM active memory systems. ...
The dirty bit is set when a memory line is cached by one processor in the exclusive state. ...
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