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NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm

A. Kalimuthu, M. Karthikeyan
2018 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction.  ...  In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC  ...  The NoC became an efficient approach to the conventional bus based design for inter core communication. In [1] , Network on Chip (NoC) is realized through the use of Torus structure.  ... 
doi:10.11591/ijres.v6.i2.pp105-110 fatcat:vqliyfkyxzetriotfmdyhru3oe

Effective Routing Algorithm and Topology on Power Consumption in Networks on Chip

Mehdi Taassori
2018 Journal of Computers  
We assess the impact of deterministic, partially adaptive and fully adaptive routing algorithms and also mesh and torus topologies with and without using low power encoding algorithm on link and total  ...  This paper illustrates the efficacy of low power encoding approach on power consumption in on chip networks.  ...  Dara Rahmati due to using Persian tool as a NoC infrastructure as well as editors and the referees of the journal.  ... 
doi:10.17706/jcp.13.2.204-211 fatcat:35ltiuvrhvfxva3ps5lb7z6ssq

An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models

M. Mirza-Aghatabar, S. Koohi, S. Hessabi, M. Pedram
2007 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)  
NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip.  ...  In this paper, we compare two popular NoC topologies, i.e., mesh and torus, in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms  ...  Although partially adaptive routing algorithms have more adaptivity than the deterministic algorithm, they do not distribute the data traffic in a network any better than the deterministic one.  ... 
doi:10.1109/dsd.2007.4341445 dblp:conf/dsd/Mirza-AghatabarKHP07 fatcat:pwtopbf7kne5nmkaicdtiim7xa

A Survey for Silicon on Chip Communication

K. Ashok Kumar, P. Dananjayan
2017 Indian Journal of Science and Technology  
Objectives: Network on Chip (NoC) has been emerging area as communication is very complex at Chip Multi Processor and it has become more popular due to its high bandwidth and improved performance than  ...  The routing algorithms are given based on adaptively which finds the shortest distance from source to destination.  ...  Figure 7 . 7 Classification of the routing algorithms in NoC. . 2. Depend on adapting (deterministic, oblivious and adaptive) 23 . 3.  ... 
doi:10.17485/ijst/2017/v10i1/110286 fatcat:rytgznvryjbc3mau7e5xgkaf6i

DESIGN AND READ STABILITYANALYSIS OF 8T SCHMITT TRIGGER BASED SRAMDESIGN OF FIVE PORT PRIORITY BASED ROUTER WITH PORT SELECTION LOGIC FOR NoC

Meenu Anna George, Aravindhan A, Lakshminarayanan G
2017 ICTACT Journal on Microelectronics  
For effective global on-chip communication, routers provide efficient routing with comparatively low complexity and high performance.  ...  Network-on-chip (NoC) is a relatively new technology to signaling that enables not only more efficient interconnects but also more efficient design and verification processes for modern SoCs.  ...  ACKNOWLEDGEMENT The authors would like to thank Facility for Advanced Computing, testing and Simulation of Electronic circuits (FACTS ElCi) for providing lab facility for our research work.  ... 
doi:10.21917/ijme.2017.0051 fatcat:2vpzn4leffe6xebshyh6cdz3ne

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects

Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan, Chita R. Das
2006 2006 1st International Conference on Nano-Networks and Workshops  
However, increasingly diminishing feature sizes have rendered the interconnect as the primary bottleneck in terms of both latency and power consumption in on-chip systems.  ...  The notion of a Network-on-Chip (NoC) is rapidly gaining a foothold as the communication fabric in complex System-on-Chip (SoC) architectures.  ...  Specifically, in deterministic routing, EDP is lowered by 47% and 63% (on average) in TORUS and MESH, respectively. In adaptive routing, MEP lowers EDP by 50%, on an average, in both TORUS and MESH.  ... 
doi:10.1109/nanonet.2006.346214 dblp:conf/nanonet/ParkNKVD06 fatcat:zt7g4kdshvfuxc44wrtyn43azu

A low latency router supporting adaptivity for on-chip interconnects

Jongman Kim, Dongkook Park, T. Theocharides, N. Vijaykrishnan, Chita R. Das
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
As a potential solution to these limitations, Networks-on -Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip.  ...  We simulate and evaluate the proposed architecture in terms of network latency and energy consumption.  ...  In this section, we present a customized router architecture that can support deterministic, and adaptive routing in 2-D mesh and torus on-chip networks.  ... 
doi:10.1145/1065579.1065726 dblp:conf/dac/KimPTVD05 fatcat:vza4yoj2anfa3hebi5ufetdlhu

A low latency router supporting adaptivity for on-chip interconnects

Jongman Kim, Dongkook Park, T. Theocharides, N. Vijaykrishnan, C.R. Das
2005 Proceedings. 42nd Design Automation Conference, 2005.  
As a potential solution to these limitations, Networks-on -Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip.  ...  We simulate and evaluate the proposed architecture in terms of network latency and energy consumption.  ...  In this section, we present a customized router architecture that can support deterministic, and adaptive routing in 2-D mesh and torus on-chip networks.  ... 
doi:10.1109/dac.2005.193873 fatcat:hm7yyllfovhfrhjzijp43xvuum

A Proficient Performance Scrutiny of King Mesh Topology based on the Routing Algorithms

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
The number of cores in a System on Chip (SoC) increases gradually in the pre-decades and affect the system performance.  ...  Network on Chip (NoC), is an associate degree approach to construct the interaction between subsystems.  ...  The main categories of network routing algorithms are Oblivious, Deterministic and Adaptive algorithms.  ... 
doi:10.35940/ijitee.g5329.078919 fatcat:kuparnzppvds5edylikijyprlq

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Misbah Manzoor, Roohie Naaz Mir, Najeeb-ud-Din Hakim
2021 Scalable Computing : Practice and Experience  
Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs.  ...  Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication.  ...  Communication in Multi-Processor System on Chips (MPSoCs) became a much costly asset than computation. Hence new communication architecture was needed and thus Network-on-chip (NoC) was welcomed.  ... 
doi:10.12694/scpe.v22i3.1896 fatcat:yx6gjwkqojh4zkactqkxjmwoge

Review of Network on Chip Routing Algorithms

Khurshid Ahmad, Muhammad Sethi
2020 EAI Endorsed Transactions on Context-aware Systems and Applications  
Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC). In NoC architecture node/ component of MPSOC are communicating through a network.  ...  The performance of NoC architecture depends on topology, routing algorithm and switching technique.  ...  OE and 3DEP are partial adaptive routing algorithm [29, 30] . DyAD and FA-DyAD are adaptive and deterministic [31, 32] . The deterministic routing algorithms are FTXY and ZigZig [33, 34] .  ... 
doi:10.4108/eai.23-12-2020.167793 fatcat:c6mclrcc6fdwlptq3sh4s33qdy

Performance Analysis of Minimum Hop Source Routing Algorithm for Two Dimensional Torus Topology NOC Architecture under CBR Traffic

Dinesh Lekariya
2013 IOSR Journal of Electronics and Communication Engineering  
Network on Chip has emerged as new paradigm for the system designers to design an on chip interconnection network.  ...  Performance of NOC network in terms of latency and throughput for minimum hop source routing algorithm is also evaluated.  ...  Wei Luo and Dong Xiang [5] have proposed in their paper an efficient adaptive deadlock free routing algorithm for torus network. Ran Manevich et al.  ... 
doi:10.9790/2834-0720512 fatcat:sudzb6xqkvbwtpi4v2ig6ahboe

Performance evaluation of Butterfly on-Chip Network for MPSoCs

Mohammad Arjomand, Hamid Sarbazi-Azad
2008 2008 International SoC Design Conference  
Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges.  ...  In this paper, we evaluate Butterfly network with arbitrary extra stages as MPSoC infrastructure. Different routing and switching strategies are used for architectural consideration.  ...  NoCs use both deterministic or adaptive routing and different switching strategies to route packet.  ... 
doi:10.1109/socdc.2008.4815631 fatcat:zlxshmmbu5chtlmdhe2k3heimy

Adaptive Virtual Cut-Through as a Viable Routing Method

Ho Won Kim, Hyun Suk Lee, Sunggu Lee, Jong Kim
1998 Journal of Parallel and Distributed Computing  
Adaptive virtual cut-through is considered as a viable alternative to wormhole switching for fast and hardware-efficient interprocessor communication in multicomputers.  ...  A network interface controller chip, which is crucial to our adaptive virtual cut-through method, has also been designed and is under fabrication. 1998 Academic Press, Inc.  ...  Third, fully adaptive routing in torus networks is difficult and requires extra virtual channels to be used for deadlock avoidance.  ... 
doi:10.1006/jpdc.1998.1466 fatcat:kna74qb66fecvohloatq3xajue

Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction [chapter]

Isiaka A. Alimi, Romil K. Patel, Oluyomi Aboderin, Abdelgader M. Abdalla, Ramoni A. Gbadamosi, Nelson J. Muga, Armando N. Pinto, António L. Teixeira
2022 Network-on-Chip - Architecture, Optimization, and Design Explorations  
Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems.  ...  In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements.  ...  projects DSPMetroNet (POCI-01-0145-FEDER-029405) and UIDB/50008/2020-UIDP/50008/2020 (DigCORE), and by FCT/MCTES through national funds and when applicable co-funded EU funds under the project UIDB/50008  ... 
doi:10.5772/intechopen.97262 fatcat:ldlwtoy5nbgfpdmokhimzsesby
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