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Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

Myint Wai Phyu, Kangkang Fu, Wang Ling Goh, Kiat-Seng Yeo
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
PROPOSED DUAL-EDGE TRIGGERED FLIP-FLOPS In this section, two new dual edge-triggered sense-amplifier flip-flops are constructed and discussed.  ...  Dual Edge-Triggered Static-Pulsed Flip-Flop The dual-edge triggered static pulsed flip-flop (DSPFF) is shown in Fig. 2 .  ... 
doi:10.1109/tvlsi.2009.2029116 fatcat:vdn4riqvkjg2bfc7m3m4rlng7i

Efficient Explicit Pulsed Double Edge Triggered Flip-Flop by Using Dependency on Data

Tania Gupta
2012 IOSR Journal of Electronics and Communication Engineering  
This paper compares three existing design of dual edge triggered flip-flop EP_CDFF, EP_CPFF and DET-SAFF with the proposed design of the dual edge triggered flip-flop (DET-FF).  ...  Dual edge triggering is an emerging effective method for reducing the power consumption in the clock distribution network.  ...  In the proposed work dual edge triggering is combined with the sense amplifier approach and data dependent technique for reducing power consumption.  ... 
doi:10.9790/2834-0210107 fatcat:z4kw4grfjfhxvautwmf4gxctpq

Design of Novel Low Power Dual Edge Triggered Flipflop

M. Jasmin
2015 Indian Journal of Science and Technology  
This paper aims in the design of novel low power flip-flop which is an important element to determine the performance of the synchronous circuit in the area of low power VLSI.  ...  High speed Computing and processing applications also requires low power designs to enhance their performance. Flip-flops are the basic memory and timing elements in digital circuits.  ...  In this Dual Edge Triggered Static Flip Flop (DSPFF) consumes less power when compare to Static Output Controlled Discharge Flip-Flop (SCDFF), Adaptive Clocking Edge Sense Amplifier Flip-Flop (ACSAFF).  ... 
doi:10.17485/ijst/2015/v8i32/89091 fatcat:v5luimmlxfbe5ipf36nlzh3lwa

An explicit-pulsed double-edge triggered JK flip-flop

Yanyun Dai, Jizhong Shen
2009 2009 International Conference on Wireless Communications & Signal Processing  
This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance.  ...  The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops.  ...  Proposed Dual Edge Triggered Flip Flop: The proposed The pulse generator of explicit pulsed flip flop is shared D Flip Flop shown in Fig. 1 consists of an input and by neighbouring flip flops [12] Fig  ... 
doi:10.1109/wcsp.2009.5371580 fatcat:ktwjkqnegnetflsxbt5mgszrti

High Performance Low Power Dual Edge Triggered Static D Flip-Flop

Gagandeep Singh, Gurmohan Singh, Vemu Sulochna
2013 International Journal of Electrical and Computer Engineering (IJECE)  
In this paper a low-power double-edge triggered static flip-flop (DETSFF) suitable for low-power and high performance applications is presented.  ...  Comparison with some of the latest DETFFs shows that the proposed DETSFF can achieve the lowest power consumption, lowest clock to Q delay and thus Power-delay-product (PDP).  ...  Figure 1 . 1 Dual-edge triggered static pulsed Flip-flop structure Figure 2 . 2 Dual edge-triggered Sense Amplifier flip-flop (DESAFF): (a) Dual pulse generator (b) Sense amplifier flip flop (c) Low  ... 
doi:10.11591/ijece.v3i5.3164 fatcat:x5yeo6xj6rb6fpzcfng3zlxal4

High-performance and low-power conditional discharge flip-flop

Peiyi Zhao, T.K. Darwish, M.A. Bayoumi
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.  ...  A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology.  ...  Another edge-triggered flip-flop is the sense amplifier based flip-flop (SAFF) [6] . All these hard-edged flip-flops are characterized by positive setup time, causing large -to-delays.  ... 
doi:10.1109/tvlsi.2004.826192 fatcat:p5ptd75skjbs3iq2scshsalola

High Speed High Capacity Memories for Secured Internet of Things based systems

2020 International Journal of Advanced Trends in Computer Science and Engineering  
Dual Edge Triggering (DET) flip-flops stand out to be a unique solution overcoming the trade-offs between speed and power.  ...  The two designs are compared with existing 16 Transistor (16T) DET Flip-Flop. 14T DETFF (Dual Edge Triggered Flip-Flop) is found to be efficient in terms of area power and delay parameters. 12T DETFF shows  ...  (DSPFF) [33] , and the adaptive clocking dual-edge triggered sense amplifier flip-flop (ACSAFF) are few Dual Edge triggered flip-flops which act on the principle of Differential amplifier.  ... 
doi:10.30534/ijatcse/2020/273952020 fatcat:orfawvzivfalrnqgujbgb4ua4q

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-CMOS, double edge, flip-flop, low power.  ...  In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced.  ...  Traditional master-slave single-edge flip-flops [7] - [9] are made up of two stages, one master and one slave. Another edge-triggered flip-flop is the sense amplifier based flip-flop, SAFF [10] .  ... 
doi:10.1109/tvlsi.2007.893623 fatcat:rggho5otlfcqldra3imm343hcu

Edge-Triggered Pulsed Sequential Elements with SoC Applications

Ch. Lavanya, N. Gopichand, L. Srinivas
2016 International journal of computer and communication technology  
In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.  ...  To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved.  ...  Another edge-triggered flip-flop is the sense amplifier-based flipflop (SAFF) [4] . All of these hard edged-flip-flops are characterized by a positive setup time, causing large Dto-Q delays.  ... 
doi:10.47893/ijcct.2016.1353 fatcat:vpmp3scbnjamjlauwgd33oiwfy

A Fully Static True-Single-Phase-Clocked Dual-Edge-Triggered Flip-Flop for Near-Threshold Voltage Operation in IoT Applications

Yongmin Lee, Gicheol Shin, Yoonmyung Lee
2020 IEEE Access  
INDEX TERMS Flip-flop, dual-edge-triggered (DET), single phase, low power, near-threshold voltage.  ...  A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper.  ...  An example of a pulsed-latch-type DET-FF with explicit pulse is the Sense-Amplifier DET flip-flop (SA-DET FF) [11] shown in Fig. 2(b) .  ... 
doi:10.1109/access.2020.2976773 fatcat:5h73guxnffdkrdwgwd4esgouwe

Design of Sequential Elements for Low Power Clocking System

Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, Zhongfeng Wang
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. Index Terms-Flip-flop, low power.  ...  To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved.  ...  Another edge-triggered flip-flop is the sense amplifier-based flip-flop (SAFF) [4] . All of these hard edged-flip-flops are characterized by a positive setup time, causing large D-to-Q delays.  ... 
doi:10.1109/tvlsi.2009.2038705 fatcat:kilj5utsybffjfnptmkivlbdz4

Clocking and clocked storage elements in a multi-gigahertz environment

V. G. Oklobdzija
2003 IBM Journal of Research and Development  
We explain how to compare different clocked storage elements with each other, and discuss issues related to power consumption and low-power designs.  ...  generator stage of the sense amplifier flip-flop.  ...  Figure 17 Dual 17 -edge-triggered (DET) CSEs: (a) Latch-mux. (b) Flip-flop topology. (c) Dual-edge-triggered flip-flop (DETFF). Reprinted from [33] with permission; © 2002 IEEE.  ... 
doi:10.1147/rd.475.0567 fatcat:6mfm5sy4abdqrjopswlivundby

Low Power and Energy Efficient Asynchronous Design

Peter A. Beerel, Marly E. Roncken
2007 Journal of Low Power Electronics  
This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts.  ...  We also thank Ivan Sutherland for helping us use the terms "energy" and "power" consistently, and for accepting-to his regret-our use of "open" and "closed" for latches.  ...  It consists of three analog components: a sensor transistor senses the current drawn by the computation and converts this to a low-swing voltage signal, which is amplified by an AC-coupled sense amplifier  ... 
doi:10.1166/jolpe.2007.138 fatcat:erlvur724ngp7bzbuluf2yn3se

Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs

Shaolan LI, Arindam SANYAL, Kyoungtae LEE, Yeonam YOON, Xiyuan TANG, Yi ZHONG, Kareem RAGAB, Nan SUN
2019 IEICE transactions on electronics  
They have the merits of simple, highly digital and low-voltage tolerant, making them attractive alternatives for the classic scaling-unfriendly operational-amplifier-based methodology.  ...  The first and most straightforward phase quantizer is to use an edge-triggered counter, as illustrated in Fig. 4 .  ...  It exploits TD variables such as frequency, phase and delay in lieu of voltage to process analog signal in simple digital-like circuits (e.g., flip-flops and inverters), thus allowing analog circuits to  ... 
doi:10.1587/transele.2018cti0001 fatcat:nonxkbob5rc57iw4af4psapv7e

COMPARISON OF CONDITIONAL TECHNIQUES FOR IMPLICIT AND EXPLICIT PULSED-TRIGGERED FLIP-FLOPS IN TERMS OF POWER AND DELAY

Lalita Gupta, Mrs Mangesh
unpublished
The simulation is carried out by TANNER EDA TOOL using 180 nm CMOS technology, 1.8V power supply and clock frequency of 250MHz is used for Single edge triggered whereas 150MHz used for double edge triggered  ...  Flip-Flops.  ...  EXPLICIT PULSE TRIGGERED FLIP FLOP Pulse triggered flip-flop( Soft -edged) outperform the Master-slave flip-flop (Hard-edged) flip-flop as they provide negative setup time and small D-to-Q delays which  ... 
fatcat:ec7f3nl2enfkzauu7b7pmhiysm
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