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Power-Efficient DRAM Speculation

Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith
2008 High-Performance Computer Architecture  
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based shared memory multiprocessor systems that speculatively access DRAM in parallel with the broadcast snoop.  ...  Although speculatively accessing DRAM has the potential performance advantage of overlapping DRAM latency with the snoop, it wastes power for memory requests that obtain data from other processors' caches  ...  Power-Efficient DRAM Speculation Power-Efficient DRAM Speculation (PEDS) is a new optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM before the  ... 
doi:10.1109/hpca.2008.4658649 dblp:conf/hpca/AggarwalCLS08 fatcat:4npkvocmfnajlnu6klbuiqtkm4

A Predictor-Based Power-Saving Policy for DRAM Memories

Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben Juurlink, Kees Goossens
2012 2012 15th Euromicro Conference on Digital System Design  
DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies.  ...  One of the most power-hungry components is the off-chip DRAM, even when it is idle.  ...  Efficient Power-Saving Mode Selection Selecting the best power-saving mode depends on the length of the idle period.  ... 
doi:10.1109/dsd.2012.11 dblp:conf/dsd/ThomasCAJG12 fatcat:6xa2x76oovbxrfirhlccvz2cqi

Reducing DRAM row activations with eager read/write clustering

Myeongjae Jeon, Conglong Li, Alan L. Cox, Scott Rixner
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
dirty cache lines to DRAM.  ...  Reducing DRAM Row Activations with Eager Writeback by Myeongjae Jeon This thesis describes and evaluates a new approach to optimizing DRAM performance and energy consumption that is based on eagerly writing  ...  In designing energy efficient DRAM, the dynamic power consumption has become a much more important concern than the static power consumption.  ... 
doi:10.1145/2541228.2555300 fatcat:ipm5knaeuzepvmmhdx3y5kshxe

Exploring energy-performance-quality tradeoffs for scientific workflows with in-situ data analyses

Georgiana Haldeman, Ivan Rodero, Manish Parashar, Sabela Ramos, Eddy Z. Zhang, Ulrich Kremer
2014 Computer Science - Research and Development  
/energy tradeoffs of different data movement strategies and how to balance these tradeoffs with quality of solution and data speculation.  ...  Power and energy are critical concerns for high performance computing systems from multiple perspectives, including cost, reliability/resilience and sustainability.  ...  Efficiently speculating about data transfers within this deep memory hierarchy requires understanding its possible impact on performance as well as on energy/power for each of the levels of the memory  ... 
doi:10.1007/s00450-014-0268-6 fatcat:guukjr2c5jfktow545gkydta2u

GhostKnight: Breaching Data Integrity via Speculative Execution [article]

Zhi Zhang, Yueqiang Cheng, Yinqian Zhang, Surya Nepal
2020 arXiv   pre-print
We observe that the speculative execution not only leaves traces in the microarchitectural buffers but also induces side effects within DRAM, that is, the speculative execution can trigger an access to  ...  an illegitimate address in DRAM.  ...  The loop count is minimized to maximize the efficiency of speculative DRAM access.  ... 
arXiv:2002.00524v1 fatcat:pp3w75lwujbyrg7xfgwlmyh3gy

The virtual write queue

Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
2010 SIGARCH Computer Architecture News  
We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved  ...  cpu2006, we demonstrate that the proposed Virtual Write Queue achieves an average 10.9% system-level throughput improvement on memory-intensive workloads, along with an overall reduction of 8.7% in memory power  ...  The authors acknowledge the use of the Archer infrastructure for their simulations, and Kyu-Hyoun Kim for assistance in DRAM bus utilization calculations.  ... 
doi:10.1145/1816038.1815972 fatcat:nsztbkb3ifguvkolw25vhet5dq

The virtual write queue

Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
2010 Proceedings of the 37th annual international symposium on Computer architecture - ISCA '10  
We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved  ...  cpu2006, we demonstrate that the proposed Virtual Write Queue achieves an average 10.9% system-level throughput improvement on memory-intensive workloads, along with an overall reduction of 8.7% in memory power  ...  The authors acknowledge the use of the Archer infrastructure for their simulations, and Kyu-Hyoun Kim for assistance in DRAM bus utilization calculations.  ... 
doi:10.1145/1815961.1815972 dblp:conf/isca/StuecheliKDHJ10 fatcat:hzdxcjpt6ffp7ism3xgwqsma4a

Improving System Energy Efficiency with Memory Rank Subsetting

Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber
2012 ACM Transactions on Architecture and Code Optimization (TACO)  
Their suboptimal performance and energy inefficiency can have a significant impact on system-wide efficiency since much of the system power dissipation is due to memory power.  ...  and performance at the cost of additional DRAM devices.  ...  to speculatively open or close rows, which is the case for Ahn et al. [2006] .  ... 
doi:10.1145/2133382.2133386 fatcat:ugfmjo4vajgtnk5hg6juv5vi7i

2019 Index IEEE Computer Architecture Letters Vol. 18

2020 IEEE computer architecture letters  
Yasin, A., +, LCA July-Dec. 2019 91-94 Linux Exploiting OS-Level Memory Offlining for DRAM Power Management.  ...  -June 2019 6-9 Memory management Exploiting OS-Level Memory Offlining for DRAM Power Management. Lee, S., +, LCA July-Dec. 2019 141-144 Power Profiling of Modern Die-Stacked Memory.  ... 
doi:10.1109/lca.2020.2964168 fatcat:pv44gn35vrb75jabsid7x62xpm

Minimalist open-page

Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John
2011 Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-44 '11  
Contemporary DRAM systems have maintained impressive scaling by managing a careful balance between performance, power, and storage density.  ...  The use of the "Page-mode" feature of DRAM devices can mitigate many DRAM constraints. Current open-page policies attempt to garner the highest level of page hits.  ...  DRAM Page Closure (Precharge) Policy In general, our Minimalist policy does not speculatively leave DRAM pages open.  ... 
doi:10.1145/2155620.2155624 dblp:conf/micro/KaseridisSJ11 fatcat:isqtxw73zzga5gprid2gasrnfe

Future scaling of processor-memory interfaces

Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber
2009 Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis - SC '09  
and performance at the cost of additional DRAM devices.  ...  We identify the impact of rank subsetting on memory power and processor performance analytically, then verify the analyses by simulating a chipmultiprocessor system using multithreaded and consolidated  ...  To enhance energy efficiency, memory controllers may utilize the low-power states of DRAMs when the requests from the processors are infrequent.  ... 
doi:10.1145/1654059.1654102 dblp:conf/sc/AhnJKLS09 fatcat:gvgc7gptufckjihspvodjhqbo4

Scalable Name-Based Packet Forwarding

Tian Song, Haowei Yuan, Patrick Crowley, Beichuan Zhang
2015 Proceedings of the 2nd International Conference on Information-Centric Networking - ICN '15  
The above efficient memory size produces high performance. Estimated throughput of the SRAM-and DRAM-based solutions are 284 Gbps and 62 Gbps respectively.  ...  rules based on the Alexa dataset only needs 5.58 MiB memory, which can easily fit in fast memory like SRAM, and with one billion synthetic rules it takes 7.32 GiB memory, which is within the range of DRAM  ...  ) 5.58 MiB 31.01 MiB 20 MSPS 62.02 Gbps billions w/ pipeline Mi is mebi, multiplied by a power of 1024, while M is mega with a power of 1000.  ... 
doi:10.1145/2810156.2810166 dblp:conf/acmicn/SongYCZ15 fatcat:4iuvxahxbzgadptdgdefy365bm

Power-Efficient Cache Coherence [chapter]

Craig Saldanha, Mikko H. Lipasti
2004 High Performance Memory Systems  
This paper examines the effects of reduced speculation on both performance and power consumption in a scalable snoop-based design.  ...  Snoop-based cache coherence implementations employ various forms of speculation to reduce cache miss latency and improve performance.  ...  This configuration is more power efficient because it does not speculatively transmit data, and therefore there is no power wasted to transmit useless data packets over the data interconnect.  ... 
doi:10.1007/978-1-4419-8987-1_5 fatcat:a3ugthykpnc6zev7efumbboa7y

System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs

Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
With improved performance/power trade-offs over previous generation DRAMs, Wide I/O DRAMs provide an extremely energy-efficient green memory solution required for next-generation embedded and highperformance  ...  With both industry and academia pushing to evaluate and employ these highly anticipated memories, there is an urgent need for an accurate power model targeting Wide I/O DRAMs that enables their efficient  ...  ., in [8] - [10] on the other hand, employed a similar circuit-level architecture and power model that was adapted to perform speculative designspace exploration of 3D-stacked Wide I/O DRAM memories.  ... 
doi:10.7873/date.2013.061 dblp:conf/date/0001WAWG13 fatcat:nnm34mxwrzg6zp3xxeve2jugzi

Limited bandwidth to affect processor design

D. Burger, J.R. Goodman, A. Kagi
1997 IEEE Micro  
Effect Solution P L B High-bandwidth DRAMs ↑ ? ↓ Larger on-chip caches ↑ ↓ ↓ Bandwidth-efficient requests ? ↑ ↓ More efficient caches ↑ ?  ...  More efficient on-chip caches.  ... 
doi:10.1109/40.641597 fatcat:nfsuhud2yzefrk7at6kxlwvbla
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