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Power-Aware Real-Time Scheduling upon Dual CPU Type Multiprocessor Platforms [chapter]

Joël Goossens, Dragomir Milojevic, Vincent Nélis
2008 Lecture Notes in Computer Science  
We introduce a dual CPU type multiprocessor platform model (compatible with any general-purpose processor) and a non-DVFS associated methodology which considerably simplifies the energy-aware real-time  ...  Nowadays, most of the energy-aware real-time scheduling algorithms belong to the DVFS (Dynamic Voltage and Frequency Scaling) framework.  ...  Conclusion and future work In this paper, we have addressed the energy-aware scheduling problem upon a DMP, a dual CPU type multiprocessor architecture composed of two homogeneous platforms.  ... 
doi:10.1007/978-3-540-92221-6_25 fatcat:swnec5vpvrcorlx5upbefpzibm

Effectiveness of power strategies for video applications: a practical study

Sébastien Bilavarn, Jabran Khan, Cécile Belleudy, Muhammad Khurram Bhatti
2014 Journal of Real-Time Image Processing  
Her research interests are in the general field of System-on-Chip design with a specific interest in power optimisation, including power management, low power and real time scheduling, DVFS, DPM techniques  ...  Based on real implementations of three power strategies using representative platforms and H.264 applications, we analyse platform and application level parameters affecting the operability and efficiency  ...  Deadline scheduling Energy-efficient deadline scheduling, also referred to as low power scheduling, is part of a more theoretical field of study on real time scheduling that has attracted a lot of attention  ... 
doi:10.1007/s11554-013-0394-6 fatcat:osooer3xpnbn7elqgwepkynnqq

Ada and cc-NUMA architectures what can be achieved with Ada 2005?

A. J. Wellings, A. H. Malik, N. C. Audsley, A. Burns
2010 ACM SIGAda Ada Letters  
Real-time systems are finding it difficult to make the shift from single processor systems to multiprocessors because of the lack of support from programming platforms for multiprocessors.  ...  Unfortunately, architectural complexity and tight timing constraints make the development of real-time systems on heterogeneous multiprocessor architectures extremely difficult.  ...  Real-time systems are also increasing in size and complexity. The only architectures that will be able to satisfy the needs of these applications will be multiprocessors.  ... 
doi:10.1145/1806546.1806560 fatcat:7yx7igcgwbcinfc7uke36qtip4

Energy-Efficient Task Partitioning for Real-Time Scheduling on Multi-Core Platforms

Manal A. El Sayed, El Sayed M. Saad, Rasha F. Aly, Shahira M. Habashy
2021 Computers  
This paper deals with the problem of energy-aware static partitioning of periodic, dependent real-time tasks on a homogenous multi-core platform.  ...  Multi-core processors have become widespread computing engines for recent embedded real-time systems.  ...  Partitioning-based real-time scheduling of multiprocessors finds feasibility as the primary aim.  ... 
doi:10.3390/computers10010010 fatcat:serhkrztfzgvbdg6dqngawz5wm

Global Scheduling of Multi-Mode Real-Time Applications upon Multiprocessor Platforms [article]

Vincent Nelis and Joël Goossens CISTER Research unit Polytechnic Institute of Porto
2011 arXiv   pre-print
We propose two distinct protocols that manage the mode transitions upon uniform and identical multiprocessor platforms at run-time, each specific to distinct task requirements.  ...  Multi-mode real-time systems are those which support applications with different modes of operation, where each mode is characterized by a specific set of tasks.  ...  Conclusion and open problems In this paper, we addressed the scheduling problem of multi-mode real-time applications upon identical and uniform multiprocessor platforms.  ... 
arXiv:1102.2094v1 fatcat:3n33mo62uzg6dc3cy33gfjoihe

Evaluating IA-32 web servers through simics: a practical experience

F.J. Villa, M.E. Acacio, J.M. García
2005 Journal of systems architecture  
The results we have obtained corroborate the intuition of increasing performance of a dual-processor web server opposite to a single-processor one, and at the same time, allow us to check out Simics limitations  ...  Finally, we compare these results with those that are obtained on real machines.  ...  His research interests include prediction and speculation in multiprocessor memory systems, multiprocessor-on-a-chip architectures, and power-aware cache-coherence protocol design. 1383-7621/$ -see front  ... 
doi:10.1016/j.sysarc.2004.09.003 fatcat:kwi2kcgtuzhqfml7weifxg4qci

On Best-Effort Utility Accrual Real-Time Scheduling on Multiprocessors [chapter]

Piyush Garyali, Matthew Dellinger, Binoy Ravindran
2010 Lecture Notes in Computer Science  
We consider the problem of scheduling real-time tasks on a multiprocessor system.  ...  We create a Linux-based real-time kernel called ChronOS for multiprocessors.  ...  The only multiprocessor overload real-time scheduling algorithms that we are aware of (at the time of writing this thesis) include the Multiprocessor On-Line Competitive Algorithm (or MOCA) [48] and  ... 
doi:10.1007/978-3-642-17653-1_21 fatcat:bjswbjfuijebnhotcthab5dpzy

The low power energy aware processing (LEAP) embedded networked sensor system

D. Mclntire, K. Ho, B. Yip, A. Singh, W. Wu, W.J. Kaiser
2006 2006 5th International Conference on Information Processing in Sensor Networks  
Embedded wireless networked sensor, energy-aware multiprocessor platform, sensor platform hardware and software architecture.  ...  To meet these new requirements while maintaining critical support for low energy operation, a new multiprocessor node hardware and software architecture, Low Power Energy Aware Processing (LEAP), has been  ...  The approach leads to the new Low Power Energy Aware Processing (LEAP) multiprocessor architecture for ENS nodes.  ... 
doi:10.1109/ipsn.2006.243913 fatcat:lvrumubxpbhurhgaacm6ywfg5y

Exploring the Multitude of Real-Time Multi-GPU Configurations

Glenn A. Elliott, James H. Anderson
2014 2014 IEEE Real-Time Systems Symposium  
In this paper, we explore real-time schedulability of several categories of configurations for multiprocessor, multi-GPU systems that are possible under GPUSync, a recently proposed highly configurable  ...  Motivated by computational capacity and power efficiency, techniques for integrating graphics processing units (GPUs) into real-time systems have become an active area of research.  ...  Still, few have explored multiprocessor, multi-GPU real-time systems. CPUs in traditional multiprocessor scheduling can follow a partitioned, clustered, or global approach.  ... 
doi:10.1109/rtss.2014.39 dblp:conf/rtss/ElliottA14 fatcat:q45n6opabvb4zemdgca4g5zrfy

The low power energy aware processing (LEAP)embedded networked sensor system

Dustin McIntire, Kei Ho, Bernie Yip, Amarjeet Singh, Winston Wu, William J. Kaiser
2006 Proceedings of the fifth international conference on Information processing in sensor networks - IPSN '06  
To meet these new requirements while maintaining critical support for low energy operation, a new multiprocessor node hardware and software architecture, Low Power Energy Aware Processing (LEAP), has been  ...  The LEAP architecture integrates fine-grained energy dissipation monitoring and sophisticated power control scheduling for all subsystems including sensor subsystems.  ...  The approach leads to the new Low Power Energy Aware Processing (LEAP) multiprocessor architecture for ENS nodes.  ... 
doi:10.1145/1127777.1127846 dblp:conf/ipsn/McIntireHYSWK06 fatcat:nfmofetivrgu5b6df3bgrfa3g4

A State-of-the-Art Survey on Real-Time Issues in Embedded Systems Virtualization

Zonghua Gu, Qingling Zhao
2012 Journal of Software Engineering and Applications  
sections to cover them. ) Xen-Based Solutions Cherkasova et al. [27] introduced and evaluated three CPU schedulers in Xen: BVT (Borrowed Virtual Time), SEDF (Simple Earliest Deadline First), and Credit  ...  In recent years, it has also been widely applied to real-time embedded systems with stringent timing constraints.  ...  [44] presented a communication-aware CPU scheduling algorithm and a CPU usage accounting mechanism for Xen.  ... 
doi:10.4236/jsea.2012.54033 fatcat:iiqszwe3brhjxl4ycyf6ynbp2u

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems

Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys
2016 Journal of Low Power Electronics  
This formalization is based on pragmatic power consumption models of all the tasks of the application that are derived from real measurements.  ...  This work addresses this problem and provides a contribution by seeking to improve energy efficient deployment and analysis for embedded heterogeneous multiprocessor platforms representative of current  ...  ACKNOWLEDGEMENTS This work was carried out under the Open-PEOPLE project, a platform project funded within the framework of the Embedded Systems and Large Infrastructures program (ARPEGE) from ANR, the  ... 
doi:10.1166/jolpe.2016.1448 fatcat:kdx7t4ah2zh3poznc47qn254he

A Survey of Techniques for Reducing Interference in Real-time Applications on Multicore Platforms

Tamara Lugo, Santiago Lozano, Javier Fernandez, Jesus Carretero
2022 IEEE Access  
INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.  ...  This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020.  ...  [225] presented a hardware resource contention-aware scheduling of hard real-time multiprocessor systems.  ... 
doi:10.1109/access.2022.3151891 fatcat:vutgetjua5byxczcivmw2esqtq

Operating system support for overlapping-ISA heterogeneous multi-core architectures

Tong Li, Paul Brett, Rob Knauerhase, David Koufaty, Dheeraj Reddy, Scott Hahn
2010 HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture  
Our algorithms allow applications to transparently execute and fairly share different types of cores.  ...  We have implemented these algorithms in the Linux 2.6.24 kernel and evaluated them on an actual heterogeneous platform.  ...  We define the scaled time on CPU p at real time t to be R p • t. Thus, if a task runs for x seconds on CPU p, its scaled CPU time is R p x.  ... 
doi:10.1109/hpca.2010.5416660 dblp:conf/hpca/LiBKKRH10 fatcat:grpvb2k2rzesbiuuvkew4i54a4

An Effective Dynamic Scheduling Runtime and Tuning System for Heterogeneous Multi and Many-Core Desktop Platforms

Alecio P. D. Binotto, Carlos E. Pereira, Arjan Kuijper, Andre Stork, Dieter W. Fellner
2011 2011 IEEE International Conference on High Performance Computing and Communications  
The set of five context-aware heuristics was evaluated for the scheduling of the highlevel solvers.  ...  The packages designed for these types of requirements are presented in Figure B .2. DERAF stands for Distributed Embedded Real-time Aspects Framework.  ...  Fraunhofer Institut für Graphische und Datenverarbeitung -IGD, Germany 12.2007 -10.2010 PhD Researcher at the Industrial Applications Department, with focus on applied research projects using concepts of scheduling  ... 
doi:10.1109/hpcc.2011.20 dblp:conf/hpcc/BinottoPKSF11 fatcat:bjdij42z5fe7dmfykjjj3n7p74
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