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Scan chain design for shift power reduction in scan-based testing

Jia Li, Yu Hu, XiaoWei Li
2011 Science China Information Sciences  
Keywords low power DfT, scan-based testing, test power reduction, scan chain design Citation Li J, Hu Y, Li X W. Scan chain design for shift power reduction in scan-based testing.  ...  Based on weighted transition metric (WTM), the proposed extended WTM (EWTM) that is utilized to guide the scan chain design algorithm can estimate the scan shift power in both the shift-in and shift-out  ...  This paper proposes a DfT modification technique for reducing the shift power through scan chain design.  ... 
doi:10.1007/s11432-011-4205-z fatcat:ymhd5xhtanc6rgu3bdfojutdym

Enhanced Scan Segmentation for Low Power DFT

Test cases prepared from ITC'99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison.  ...  Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT).  ...  Synopsys Design Compiler was used for design synthesis and conventional scan chains were stitched using DFT compiler.  ... 
doi:10.35940/ijitee.h7428.078919 fatcat:ghuuipxvdfcvhjcs4f3phiqjmi

A scan shifting method based on clock gating of multiple groups for low power scan testing

Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang
2015 Sixteenth International Symposium on Quality Electronic Design  
Keywords Scan-based testing, low power scan testing, shifting power reduction, design-for-testability (DFT)  ...  From the advent of very large scale integration (VLSI) design, a larger power consumption of a scan-based testing has been one of the most serious problems.  ...  Hence, it is not necessary to modify the existing compression method in order to apply the proposed method. A design and a test flows are carried out simultaneously in the design of the modern VLSI.  ... 
doi:10.1109/isqed.2015.7085417 dblp:conf/isqed/Seo0LK15 fatcat:2b45mxa7dndl3oembfcsoqhefi

Scan chain clustering for test power reduction

Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Maeding
2008 Proceedings of the 45th annual conference on Design automation - DAC '08  
An effective technique to save power during scan based test is to switch off unused scan chains.  ...  In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test.  ...  Hence, numerous methods for design for test (DFT), automated test pattern generation (ATPG) and test planning have been proposed and are employed in high-volume manufacturing to reduce test power consumption  ... 
doi:10.1145/1391469.1391680 dblp:conf/dac/ElmWIZLM08 fatcat:byctuduk2rat3istfk5ttneb3a

Scan test planning for power reduction

Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Maeding, Jens Leenstra
2007 Proceedings - Design Automation Conference  
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis.  ...  In a recent paper it has been shown that this feature can be used for reducing the power consumption during test.  ...  They do not contain any kind of design for test (DFT) and were extended with the required BIST architecture. The flip-flops of each circuit were arranged into 32 parallel scan chains.  ... 
doi:10.1145/1278480.1278614 dblp:conf/dac/ImhofZWML07 fatcat:dcfr5h5m6nd37h3gtukvuhpzq4

A Novel Architecture for Scan Cell in Low Power Test Circuitry

G. Rajesh Kumar, K. Babulu
2015 Procedia Materials Science  
Large Test data volume and High power consumption are the main problems in Design for Testability. This excessive power consumption is mainly due to switching of the scan cells.  ...  The technique proposed in this paper reduces switching activity in the scan cells there by the power consumption during testing can be reduced.  ...  In order to design such a complex circuits new design techniques should be adopted. Many design challenges are adopted for complex digital circuit design.  ... 
doi:10.1016/j.mspro.2015.06.073 fatcat:g6v4wwhu7jgcrmi276vizihw2a

Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits

Nicola Nicolici, Bashir M. Al-Hashimi
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
This paper presents a new technique for power minimization during test application in full scan sequential circuits.  ...  For example, in the case of benchmark circuit s15850 it takes ¢ 3600s in computational time and ¢ 1% in test area and test data overhead to achieve 80% savings in power dissipation.  ...  Ha of Virginia Polytechnic Institute and State University for providing ATALANTA [14] test tool.  ... 
doi:10.1145/343647.343901 fatcat:766o77rfavdvfjoqhpphgsp6ui

Low-power scan design using first-level supply gating

S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, K. Roy
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In scan-based testing, a significant fraction of total test power is dissipated in the combinational block.  ...  We implement the masking effect by inserting an extra supply gating transistor in the VDD to GND path for the first level gates at the outputs of the scan flip-flops.  ...  It is, therefore, important to ensure reduction in power dissipation during the test mode. Scan architectures represent prevalent Design for Testability (DFT) approach to test digital circuits [9] .  ... 
doi:10.1109/tvlsi.2004.842885 fatcat:hwq2k4rh2ff75ggmpo736up3ji

Techniques for Low Power and Area Optimized VLSI Testing using Novel Scan Flip-Flop

R. Jayagowri
2015 International Journal of Computer Applications  
General Terms VLSI Testing, cell level optimization, Scan flip-flop modification. Keywords Scan flip-flop, Low power test, Shift cycle, Capture cycle D SI Out(y) SE CLK op M UX Q D  ...  In this paper we proposed different methodologies and they are at cell level optimization to reduce test power.  ...  The conclusion is given in section-4. PROPOSED TECHNIQUES The major objective of our work is to reduce the power consumption of dedicated circuit for DFT in the design.  ... 
doi:10.5120/19824-1664 fatcat:3hhn5du4znai7pgix6geksy6de

A scan segment skip technique for low power test

Hayoung Lee, Junkyu Lee, Hyunyul Lim, Sungho Kang
2015 2015 International SoC Design Conference (ISOCC)  
In this paper, a scan segment skip technique is proposed to reduce power consumption by skipping segments that don't need scan in/out processes.  ...  Also, a new pattern merge algorithm is proposed for maximizing power reduction ratio.  ...  However, as the scan is used, a large power is dissipated during the test because of 1) Design-for-Testability (DFT) to reduce test complexity, not used in the functional mode but just used in the test  ... 
doi:10.1109/isocc.2015.7401669 fatcat:f6q6ykmnvbhmdmjj7relzvb4a4

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunan Enokimoto, Hans-Joachim Wunderlich
2011 IEEE/ACM International Symposium on Low Power Electronics and Design  
Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device.  ...  For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory.  ...  For these circuits, 4x, 8x and 16x broadcast-based full-scan compression DFT hardware was synthesized using a commercial Design-for-Test tool.  ... 
doi:10.1109/islped.2011.5993600 fatcat:vzstb66bkngrnievmhcyzmk4lq

A Scan Chain Adjustment Technology for Test Power Reduction

Jia LI, Yu HU, Xiaowei LI
2006 Proceedings of the Asian Test Symposium  
This paper proposes a technique to solve this problem through scan chain adjustment to eliminate unnecessary transitions in scan chains.  ...  An extended WTM (EWTM) metric is proposed to estimate dynamic power dissipation in circuit under test caused by transitions in test stimulus and response vectors.  ...  The only overhead of grouping scan cells into two scan chains is a pair of scan-in and scan-out ports, which can be neglect in VLSI designs.  ... 
doi:10.1109/ats.2006.260986 fatcat:mu5ehwu7zjabhfjor3c7hd7g3q

Enhancing delay fault coverage through low-power segmented scan

Z. Zhang, S.M. Reddy, I. Pomeranz, J. Rajski, B.M. Al-Hashimi
2007 IET Computers & Digital Techniques  
Segmented scan [17] [18] [19] [20] has been shown to be an effective technique in addressing test power issues in industrial designs [18] .  ...  Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been  ...  Excessive power may be dissipated during scan based tests due to increased switching activity in the circuit nodes caused by scan shifts as well as by capture cycles.  ... 
doi:10.1049/iet-cdt:20060135 fatcat:r3rq2juy7rhd3ptj7p7a2r7w3e

Scan Insertion on Multi Clock Design in Modern SOC's

2017 International Journal of Science and Research (IJSR)  
VLSI technology is an emerging field in the current technological due to its advancements in fields of systems architecture, design for testability (DFT) techniques for testing modern digital circuits.  ...  In this paper different scan architectures are analyzed to study the operation of Full-Scan design. The proposed design includes Full-Scan design using Muxed-D scan cell.  ...  The chart explains the comparison of power in prescan and postscan for switching power, internal power and dynamic power.  ... 
doi:10.21275/art20175689 fatcat:brpjwlmtpncwhkbzapywisulqq

A unified solution to reduce test power and test volume for Test-per-scan schemes

Shaochong Lei, Zhen Wang, Zeye Liu, Feng Liang
2010 IEICE Electronics Express  
Therefore, the switching activities both in the combinational block and in scan chains can be reduced simultaneously.  ...  This paper proposes a unified solution to reduce test power and test volume for test-per-scan schemes.  ...  That effectively reduces switching activities both in the combinational block and in scan chains of the CUT.  ... 
doi:10.1587/elex.7.1364 fatcat:rd6vkwvqjrfkvoenepcmc7mshm
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