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Power Regulation in High Performance Multicore Processors [article]

X. Chen, Y. Wardi, S. Yalamanchili
2017 arXiv   pre-print
Results of these experiments are presented in detail exposing the practical challenges of implementing provably-convergent power regulation solutions in commodity multicore processors.  ...  This paper presents, implements, and evaluates a power-regulation technique for multicore processors, based on an integral controller with adjustable gain.  ...  Thus, effective control of power dissipation is critical to the reliable and high performance operation of multicore processors.  ... 
arXiv:1709.04859v1 fatcat:3wcfv5okcfbd7pvojsmvvk7xo4

Design and optimization of on-chip voltage regulators for high performance applications

Pingqiang Zhou
2014 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)  
in high performance multicore applications.  ...  Recent progress shows that it is possible to integrate such voltage regulators on chip to improve voltage regulation, and to potentially provide better support for DVFS technique to reduce power consumption  ...  in recent high-performance multicore processors [1] - [3] .  ... 
doi:10.1109/icsict.2014.7021194 fatcat:lt3ymdqrlvafznx6otbepgmycy

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
Our scheme is designed to automatically improve the performance of applications running on heterogeneous CMOS-TFET multicores operating under a fixed power budget, without requiring any effort from the  ...  With simulations we show that our runtime scheme can enable a CMOS-TFET multicore to serve a diversity of workloads with high energy efficiency and achieve 21% average speedup over the best performing  ...  ACKNOWLEDGEMENTS This work was supported in part by NSF awards 1147388, 0903432, 0903432, 1152479, 1017882, 0702617, 0963839, 1213052 and 1017882; and SRC NRI MIND.  ... 
doi:10.1145/2380445.2380487 dblp:conf/codes/KultursaySSNKD12 fatcat:inxlux6n5vhxfdzcyb2bcatxym

Dynamic voltage frequency scaling-aware refresh management for 3D DRAM over processor architecture

J. Lim, H. Kim, H. Oh, S. Kang
2017 Electronics Letters  
To regulate the temperature of 3D-integrated systems, the power dissipation of the processor must be regulated because the processor dissipates most of the overall power in the system.  ...  Three-dimensional integrated systems that combine large-capacity dynamic random access memory (DRAM) with high-performance processors represent a promising solution to implementing high-performance computing  ...  To regulate the temperature of 3D-integrated systems, the power dissipation of the processor must be regulated because the processor dissipates most of the overall power in the system.  ... 
doi:10.1049/el.2017.1243 fatcat:kpgcwneolzen3b2ycquizmghua

A dynamic execution time estimation model to save energy in heterogeneous multicores running periodic tasks

Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Luis March, José Duato
2016 Future generations computer systems  
In addition, to improve both performance and energy savings, the industry is introducing new multicore designs such as ARM's big.LITTLE that include heterogeneous cores in the same package.  ...  since the memory system uses a different power supply.  ...  Introduction Nowadays, real-time systems are implemented of top of high-performance multicore processors due to the growing functionality demands of the applications.  ... 
doi:10.1016/j.future.2015.06.011 fatcat:xxn7n2sjzreopha5ocjyv3d7re

Dynamic task set partitioning based on balancing memory requirements to reduce power consumption

Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato
2009 Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09  
EXTENDED ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors.  ...  DVS costs in a multicore system can be reduced by sharing the same DVS regulator among the cores (global DVS).  ...  CONCLUSIONS This paper has introduced a hard real-time power-aware partitioner and scheduler for a coarse-grain multicore processor.  ... 
doi:10.1145/1542275.1542356 dblp:conf/ics/BautistaSHPD09 fatcat:3qjiwvrp4fabfbyi2m5ocrucnq

A power capping controller for multicore processors

N. Almoosa, W. Song, Y. Wardi, S. Yalamanchili
2012 2012 American Control Conference (ACC)  
This paper presents an online controller for tracking power-budgets in multicore processors using dynamic voltage-frequency scaling.  ...  Simulation results are presented for controlling power dissipation in multiple cores of an asymmetric multicore processor.  ...  MODELING AND CONTROL OF A MULTICORE POWER REGULATION SYSTEM Consider a processor driven by a supply voltage V and operating at a frequency .  ... 
doi:10.1109/acc.2012.6314995 fatcat:wlhfuyuugjdfdcdxpz2yhe35pa

Modeling of temperature scenarios in a multicore processor system

E. Glocker, D. Schmitt-Landsiedel
2013 Advances in Radio Science  
In this paper the temperature distributions of cores in a multicore system are simulated for various scenarios.  ...  </strong> In modern CMOS integrated Systems-on-Chip global temperature variations arise as well as local fluctuations in regions of high activity, resulting in the arise of local hot spots.  ...  In a multicore system, the temperature of a processor block not only depends on its own power density, but also on the power density of neighbour blocks.  ... 
doi:10.5194/ars-11-219-2013 fatcat:haopepurwfedxifg3iitxzvvze

High-Performance Energy-Efficient Multicore Embedded Computing

A. Munir, S. Ranka, A. Gordon-Ross
2012 IEEE Transactions on Parallel and Distributed Systems  
We also discuss modern multicore processors that leverage these HPEEC techniques to deliver high performance per watt.  ...  Embedded systems differ from traditional high-performance supercomputers in that power is a first-order constraint for embedded systems; whereas, performance is the major benchmark for supercomputers.  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSERC and the NSF.  ... 
doi:10.1109/tpds.2011.214 fatcat:vagqmojdsjevvc2u2ewqrcjjpq

Improving the Efficiency of Power Management Techniques by Using Bayesian Classification

Hwisung Jung, Massoud Pedram
2008 9th International Symposium on Quality Electronic Design (isqed 2008)  
This paper presents a supervised learning based dynamic power management (DPM) framework for a multicore processor, where a power manager (PM) learns to predict the system performance state from some readily  ...  each processor core in the system.  ...  data flow for each processor, and the control unit supports high-performance and power-efficient cache coherency.  ... 
doi:10.1109/isqed.2008.4479722 dblp:conf/isqed/JungP08 fatcat:422jcze3d5fdll2yt2zm3y6h6m

Multicore Based Open Loop Motor Controller Embedded System for Permanent Magnet Direct Current Motor

2012 American Journal of Applied Sciences  
Multicore processor was used to improve the speed of execution and optimize the performance of the controller.  ...  The advantage of the proposed system was optimized operational performance and low power utility.  ...  Instead of using single core processor like ARM core if we use more than one core ie., multicore processor to establish a single task, we may get better performance and very high throughput.  ... 
doi:10.3844/ajassp.2012.924.933 fatcat:jgbzjshuxbaz3h624stztkvmyi

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Prerna Saini, Ankit Bansal, Abhishek Sharma
2015 International Journal of Embedded Systems and Applications  
The relative study for multicore processor and multicore controller concludes that micro architecture based controller having multiple cores illustrates better performance in time critical multi-tasking  ...  Due to the high complexity and limitations, it is very hard to work on the application development phase on such architectures.  ...  Abhishek Sharma for their guidance and constant supervision as well as for providing necessary information regarding the project & also for their support in completing the project.  ... 
doi:10.5121/ijesa.2015.5101 fatcat:4dw5lvd25regbg4faigluz6nym

Enabling improved power management in multicore processors through clustered DVFS

T Kolpe, A Zhai, S S Sapatnekar
2011 2011 Design, Automation & Test in Europe  
In recent years, chip multiprocessors (CMP) have emerged as a solution for high-speed computing demands. However, power dissipation in CMPs can be high if numerous cores are simultaneously active.  ...  Per-core DVFS allows the greatest flexibility in controlling power, but incurs the expense of an unrealistically large number of on-chip voltage regulators.  ...  Multicore processors, or chip multiprocessors (CMP), are seeing increasing adoption as they provide a pathway to achieving high performance under power bounds [1] .  ... 
doi:10.1109/date.2011.5763052 dblp:conf/date/KolpeZS11 fatcat:qp3rnsjhpfcjfkhauhulo7v2jq

Performance Evaluation and Analysis of Parallel Computers Workload

M.Narayana Moorthi, R. Manjula
2016 International Journal of Grid and Distributed Computing  
In this paper we investigate how to tune the performance of threaded applications with balanced load for each core or processor.  ...  By running more than one task at the same time with multiple processors concurrently or parallel we can achieve high speed in our computing applications.  ...  application performance execution time and power consumption are the main metrics to consider.Execution Time (Single core) = ∑ Time (STi); i=1 to n; Execution Time (Multicore) = Max (Time (STi); i =1  ... 
doi:10.14257/ijgdc.2016.9.1.13 fatcat:ltlw4tq725bvbkga5dvf7p6dm4

A New Core Level Utilization Algorithm for Energy-Efficient Multicore Systems

2020 International Journal of Computers  
Consequently, the focus has moved from performance to energy and power consumption.  ...  Also, Design metrics depend on, the manufacturers of semiconductor chips which, have implemented multicore processors to boost the level of energy efficiency by using verified techniques for voltage and  ...  high-performance computing (HPC) systems.  ... 
doi:10.46300/9108.2020.14.7 fatcat:fn4lkkw6cba3jc2qmk2l25r3fu
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