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Power estimation approach for SRAM-based FPGAs

Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel
2000 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00  
Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex  ...  This paper presents the power consumption estimation for the novel Virtex architecture.  ...  Estimation Approach for SRAM-based FPGAsKarlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Prof.  ... 
doi:10.1145/329166.329207 dblp:conf/fpga/WeissOKSR00 fatcat:wvc2pbeggfaufcfp4xpkhctk3y

Early stage FPGA interconnect leakage power estimation

Shilpa Bhoj, Dinesh Bhatia
2008 2008 IEEE International Conference on Computer Design  
Our methods derive leakage power estimates based on predicted values of routing congestion and interconnect resource utilization.  ...  To meet stringent budgets, system architects need accurate estimates of power distribution at various design stages. In this work, we make several key contributions to FPGA leakage power estimation.  ...  FPGA Architecture Our leakage power estimation models are based on the island style FPGA architecture adopted by VPR [9] .  ... 
doi:10.1109/iccd.2008.4751898 dblp:conf/iccd/BhojB08 fatcat:djqmrljm7vh45g6h4n5c4zx7km

Integration of Spin-RAM technology in FPGA circuits

W. Zhao, E. Belhaire, Q. Mistral, E. Nicolle, T. Devolder, C. Chappert
2006 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings  
This Spin-RAM based FPGA circuit could process securely the information in low power dissipation and high speed; meanwhile all the data processed are stored permanently in the distributed Spin-RAM memory  ...  Contrary to conventional MRAM circuits we don't use a complex sense amplifier, but a simple SRAM based sense amplifier couples two MTJs per bit.  ...  The views expressed are solely those of the authors, and the other Contractors and/or the European Community cannot be held liable for any use that may be made of the information contained herein.  ... 
doi:10.1109/icsict.2006.306511 fatcat:4nw4qpz27fh5tgv7zok6s7psty

Static power model for CMOS and FPGA circuits

Anas Razzaq, Andy Ye
2021 IET Computers & Digital Techniques  
Herein, a technology-independent static power estimation model is presented, which can estimate static power with reasonable accuracy in much less time.  ...  In Ultra-Low-Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions.  ...  The approach we are using to measure the static power consumption of the FPGA Logic Element (LE) is very similar to the approach we used for the processor.  ... 
doi:10.1049/cdt2.12021 fatcat:3kury4xftnabpib3dkkbq5jgcy

Accurate power analysis for near-Vt RRAM-based FPGA

Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs.  ...  Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-Vt SRAM-based FPGA, respectively.  ...  Then we sweep the R HRS and study its impact on RRAM-based FPGA power consumption. Modified VTR flow for power estimation.  ... 
doi:10.1109/fpl.2015.7293982 dblp:conf/fpl/TangGM15 fatcat:zotflfxsnjgxdcvko7sxbb3tn4

Fine-grain leakage optimization in SRAM based FPGAs

Somsubhra Mondal, Seda Ogrenci Memik
2005 Proceedings of the 15th ACM Great Lakes symposium on VLSI - GLSVSLI '05  
Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT.  ...  In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption.  ...  [11] developed fpgaEVA-LP for power efficiency analysis of LUT table based FPGA architectures. Several techniques for reducing leakage power were proposed in the past year. Gayasen et al.  ... 
doi:10.1145/1057661.1057719 dblp:conf/glvlsi/MondalM05 fatcat:amfi6jtpb5gpfnwp52lh6nb5oq

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs

L Sterpone, L Carro, D Matos, S Wong, F Fakhar
2011 2011 Design, Automation & Test in Europe  
Power consumption is dramatically increasing for Static Random Access Memory Field Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new CAD tools are needed.  ...  Clock-gating methodologies have been applied in low power FPGA designs with only minor success in reducing the total average power consumption.  ...  The developed technique has several advantages versus previously existing power-savings techniques for SRAM-based FPGAs.  ... 
doi:10.1109/date.2011.5763128 dblp:conf/date/SterponeCMWF11 fatcat:sfg6g2b4snaf5odsvfgoaddipa

New Non-Volatile Memory Structures for FPGA Architectures

David Choi, Kyu Choi, John D. Villasenor
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.  ...  A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described.  ...  This data loss occurs not only in SRAM-based FPGAs, but also in Flash-based FPGAs, which while using Flash for some routing and computation storage, still utilize SRAM for flip-flops.  ... 
doi:10.1109/tvlsi.2008.2000461 fatcat:d6xn7staj5eelewopzni52iqmy

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach

Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
We show that for both nanoscale complementary metal-oxide-semiconductor (CMOS) [static random access memory (SRAM)] as well as emerging non-CMOS [spin torque transfer random access memory (- TTRAM)] memory  ...  Based on this observation, next we propose a content-aware application mapping approach, which tries to maximize the logic “0” or logic “1” content in the lookup tables.  ...  STTRAM MBC over conventional SRAM-based FPGA.  ... 
doi:10.1109/jetcas.2011.2165232 fatcat:tlnx3mng3remfghm4fgulfd27u

Closed-loop modeling of power and temperature profiles of FPGAs

Kanupriya Gulati, Sunil P. Khatri, Peng Li
2009 Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '09  
In this paper, we develop a framework to model this situation in an FPGA context.  ...  At the very least, this may cause the temperature and power consumption of the IC to be poorly estimated by traditional thermal or power modeling techniques.  ...  Upon startup, as Vdd ramps up to its final voltage, the unknown state of SRAM cells in an SRAM-based FPGA can cause a current spike known as inrush current.  ... 
doi:10.1145/1508128.1508207 dblp:conf/fpga/GulatiKL09 fatcat:xd54t3olm5cetf5mxot5vz4fke

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Q. Liu, G.A. Constantinides, K. Masselos, P.Y.K. Cheung
2009 IET Computers & Digital Techniques  
To aid data reuse design exploration early during the design cycle, we present an optimization approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based  ...  Contemporary FPGA-based reconfigurable systems have been widely used to implement data dominated applications.  ...  For our experiments, we model the power based on the Celoxica RC300 platform [22] , which is equipped with a Xilinx Virtex II FPGA and ZBT SRAMs.  ... 
doi:10.1049/iet-cdt.2008.0039 fatcat:eqpgfd75cbgltcqho26op6d63e

A study on buffer distribution for RRAM-based FPGA routing structures

Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)  
By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based  ...  This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs.  ...  In SRAM-based structures, B 1 demonstrates the best timing performance which means that reducing the number of buffers for these FPGAs is not a useful approach.  ... 
doi:10.1109/lascas.2015.7250433 dblp:conf/lascas/OmamTGM15 fatcat:7wil4mkbcjf63ogzxsogchrd54

FPGA-SPICE: A simulation-based power estimation framework for FPGAs

Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2015 2015 33rd IEEE International Conference on Computer Design (ICCD)  
Mainstream Field Programmable Gate Array (FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models.  ...  In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language  ...  CONCLUSION This paper introduces a simulation-based power estimation framework for FPGAs, called FPGA-SPICE.  ... 
doi:10.1109/iccd.2015.7357183 dblp:conf/iccd/TangGM15 fatcat:53xm2rjlunef5lp2eghtcvobry

Wiring requirement and three-dimensional integration of field-programmable gate arrays

Arifur Rahman, Shamik Das, Anantha Chandraksan, Rafael Reif
2001 Proceedings of the 2001 international workshop on System-level interconnect prediction - SLIP '01  
Based on system-level modeling, we find that in FPGAs with 20K 4-input look-up tables, the reduction in channel width, interconnect delay, and power dissipation can be over 50% by 3-D implementation.  ...  In this paper analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for 3-D implementation of FPGAs are examined.  ...  In the next sections, a system-level modeling framework will be presented to estimate some of these performance metrics for conventional (2-D) SRAM-based FPGAs.  ... 
doi:10.1145/368640.368739 dblp:conf/slip/RahmanDCR01 fatcat:5zbte4ss5vgaldeb6xhpxzch2q

Efficient FPGAs using nanoelectromechanical relays

Chen Chen, H.-S. Philip Wong, Subhasish Mitra, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J Provine, David Lewis, Jeff Watt, Roger T. Howe
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
path delay reduction compared to traditional SRAM-based CMOS FPGAs at the 22nm technology node.  ...  Hysteresis characteristics of NEM relays can be utilized for designing programmable routing switches in FPGAs without requiring corresponding routing SRAM cells.  ...  Amit Lal for their support. We would also like to thank Prof. Deming Chen of the University of Illinois at Urbana-Champaign for his comments on the paper.  ... 
doi:10.1145/1723112.1723158 dblp:conf/fpga/ChenPPCAPLWHWM10 fatcat:rxpszxvuwfbern6llovihe6u4u
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