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Low power synthesis of sum-of-products computation

K. Masselos, S. Theoharis, P.K. Merakos, T. Stouraitis, C.E. Goutis
2000 ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)  
Novel techniques for the power efficient synthesis of sum-ofproduct computations are presented. Simple and efficient heuristics for scheduling and assignment are described.  ...  The partly static nature of the proposed cost functions reduces the time of the synthesis procedure.  ...  Larger reductions are achieved in the case of the carry save array multiplier. CONCLUSIONS Novel data path synthesis techniques for sum-of-products computation have been presented.  ... 
doi:10.1109/lpe.2000.155288 fatcat:nv3xub26arbdxp7zfhquexyqqa

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products

Sabyasachi Das, Sunil P. Khatri
2008 21st International Conference on VLSI Design (VLSID 2008)  
reduction of the BitClusters and selectiveinversion based computation of the final sum result.  ...  In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, the arithmetic Sum-of-Product (SOP) is an important and computationally intensive operation, consuming a significant amount  ...  These post-routing data confirm our conclusion about the area and power efficiency of our approach.  ... 
doi:10.1109/vlsi.2008.18 dblp:conf/vlsid/DasK08b fatcat:lqadjtg7pratbipodp63euxjva

Distributed arithmetic based non recursive filter for high throughput and low power applications

R. Sathiyapriya, K. Hariharan
2014 Contemporary Engineerng Sciences  
First, the efficient pipelined distributed arithmetic technique has been proposed here, it achieves low power and reduced switching activity than the conventional one.  ...  The proposed work demonstrates a design of adaptive nonrecursive filter design based on distributed arithmetic technique.  ...  In the conventional distributed arithmetic based adaptive FIR filter of order length 4, it consists of product block for to compute the partial sums for 0<l<15 and this sum of products are stored in an  ... 
doi:10.12988/ces.2014.4212 fatcat:wjeir7k7oree7f3whrcdarjxxu

Area-Delay and Energy Efficient Multi-operand Binary Tree Adder

Sujit Patel, Subodh Singhal
2020 IET Circuits, Devices & Systems  
The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among  ...  The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA.  ...  DAT: data arrival time, MOA: multi-operand adder, energy = DAT × power.  ... 
doi:10.1049/iet-cds.2019.0443 fatcat:g4rqounwifhnhg2f27vzsc3efe

Optimization of Adaptive Fir Filter for High Throughput, Low Power & Area Using Distributed Arithmetic

Kalaiarashi K, Mr.Santhakumar K
2014 IOSR Journal of VLSI and Signal processing  
The DA-based inner-product computation by conditional signed carrysave accumulation is replaced with CSA Binary to Excess-1 Converter (BEC) in order to reduce the sampling period and area complexity.  ...  This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA).  ...  The direct form configuration on the forward path of the FIR filter results in a long critical path due to an inner-product computation to obtain a filter output.  ... 
doi:10.9790/4200-04126974 fatcat:fmx3ftdb7neizodchs3lh7weny

Low Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously.  ...  This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture.  ...  Forward path becomes the critical path because of inner-product block which results in the desired output.  ... 
doi:10.35940/ijitee.j9219.0881019 fatcat:gzss4gi5lvggfcectuxfdc4iua

Resource sharing among mutually exclusive sum-of-product blocks for area reduction

Sabyasachi Das, Sunil P. Khatri
2008 ACM Transactions on Design Automation of Electronic Systems  
In state-of-the-art digital designs, arithmetic blocks consume a major portion of the total area of the IC. The arithmetic sum-of-product (SOP) is the most widely used arithmetic block.  ...  This architecture can be used in the nontiming-critical paths of the design, to save significant amounts of area.  ...  Khatri the non-timing-critical path (also called area-critical path). The sum-of-product (SOP) is the most widely used arithmetic block. Some examples of SOP are 51:2 Table I .  ... 
doi:10.1145/1367045.1367060 fatcat:3mckq4lsqnh57g2n5xhqufywd4

Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications [chapter]

S. Sivasaravanababu, T.R. Dineshkumar, G. Saravana Kumar
2021 Advances in Parallel Computing  
The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction.  ...  Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational  ...  are used at different stages of data propagation, as shown in Figure 3 .  ... 
doi:10.3233/apc210289 fatcat:4rdox7r42ba3lpomkflacodfbq

Architectural Power Estimation Based on Behavior Level Profiling

Srinivas Katkoori, Ranga Vemuri
1998 VLSI design (Print)  
for the three different parts of RTL designs, namely, data path, controller and interconnect are presented.  ...  If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation  ...  Acknowledgements This work is done at the University of Cincinnati and is supported in part by the Solid State  ... 
doi:10.1155/1998/93106 fatcat:dbj3fnjmjncxvh4uli5dm56niu

A methodology for synthesis of data path circuits

A. Chowdhary, R.K. Gupta
2002 IEEE Design & Test of Computers  
Acknowledgments We thank Sudhakar Kale, Bobby Wong, Kanchana Sridhar, and William Lock, from Intel, for helping us develop a data path synthesis system based on the methodology presented here.  ...  We have developed a new methodology for fast, efficient synthesis of data path circuits.  ...  The increasing size and complexity of VLSI processors make automated synthesis of data path logic crucial to meeting design productivity goals.  ... 
doi:10.1109/mdt.2002.1047748 fatcat:cjgri6arnzdrhkjwnp4q7m7dxy

Approximate computing: An emerging paradigm for energy-efficient design

Jie Han, Michael Orshansky
2013 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)  
Approximate computing has recently emerged as a promising approach to energy-efficient design of digital systems.  ...  Approximate computing relies on the ability of many systems and applications to tolerate some loss of quality or optimality in the computed result.  ...  Fig. 4 . 4 Power and precision tradeoffs as given by the power consumption per bit and the NED of a full adder design [44] . The product of power per bit and NED is shown by a dashed curve.  ... 
doi:10.1109/ets.2013.6569370 dblp:conf/ets/HanO13 fatcat:wimm6r5hnneo5ltdwtrw5lztvu

Radix-2 Pipelined FFT Processor with Gauss Complex Multiplication Method and Vedic Multiplier

Vamshipriya Bogireddy, P. Augusta Sophy
2015 International Journal of Engineering Research and  
In this paper an efficient 16-point DIF-FFT processor is designed by employing different low power techniques at various levels of design abstraction i.e, pipelining method at architectural level, Gauss  ...  Because of the relatively greater complexity, the power dissipation in digital signal processing (DSP) applications is of special significance, and low power design technique, are now emerging.  ...  Gunitasamuchyah which mean "The product of the sum is equal to the sum of the product". 16. Gunakasamuchyah which mean "The factors of the sum is equal to the sum of the factors".  ... 
doi:10.17577/ijertv4is041395 fatcat:qrxikqvkmrfnrglybkvy4x3czq

Comparative Analysis and Efficient VLSI Implementation of FIR Filter
English

MAHESH KADAM, KISHOR SAWARKAR, SUDHAKAR MANDE
2014 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
The design of digital filter characterized by minimum critical path and latency, low cost and reduced complexity.  ...  Using combination of pipeline and parallel processing power consumption can further reduced.  ...  respect to those in a direct form filter, to accommodate the relatively long bit strings representing sums of products on the output path.  ... 
doi:10.15662/ijareeie.2014.0307030 fatcat:6p5yp5nxlrhxjn72jou72eazsa

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans
2015 2015 Euromicro Conference on Digital System Design  
At the same time, strict power dissipation budgets and growing interest in high performance battery-powered devices drive the need for energy-efficient high performance circuits.  ...  This paper proposes a synthesis flow to enable the description and enforcement of relative timing constraints at both logic and physical synthesis levels, using the Synopsys framework and a set of in-house  ...  This measure correlates to energy efficiency as it accounts for power and time to compute the product jointly.  ... 
doi:10.1109/dsd.2015.104 dblp:conf/dsd/GibilukaMC15 fatcat:uhpwvgkqyzghdgnw5yfek6c2da

Improving energy efficiency of functional units by exploiting their data-dependent latency

Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
Critical paths of the circuits are usually sensitized by very specific data sequences, and computation time of most data sequences is smaller than clock period.  ...  For the increasing demand of portable devices and high computing power requirement for the multimedia and communication applications, the energy reduction now has become a major issue in the circuit design  ...  The total power consumption of the CMOS is the sum of its three components.  ... 
doi:10.1109/iscas.2010.5537593 dblp:conf/iscas/OuLLL10 fatcat:xwprlmatcfdtbbqvxpedkvx6wq
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