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An efficient collaborative filtering algorithm using SVD-free latent Semantic indexing and particle swarm optimization

Amira Abdelwahab, Hiroo Sekiya, Ikuo Matsuba, Yasuo Horiuchi, Shingo Kuroiwa, Masafumi Nishida
2009 2009 International Conference on Natural Language Processing and Knowledge Engineering  
Also, the SVD-free extremely reduce the time and memory usage required for dimensionality reduction employing the partial symmetric Eigenproblem.  ...  Consequently, Recommender Systems (RS) which are considered as powerful tools for Information Retrieval (IR), can access these available information efficiently.  ...  Although the PSO algorithm is a powerful optimization technique it is not applied in such problem before.  ... 
doi:10.1109/nlpke.2009.5313754 dblp:conf/nlpke/AbdelwahabSMHKN09 fatcat:3c6nrl67czh65ccoq3egt3h2mu

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor

T. SEKI
2005 IEICE transactions on electronics  
in Personal Information Management scheduler application and 40% power reduction in MPEG4 movie playback.  ...  The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of 5 mV, achieving 82% power reduction  ...  Hagiwara for help, suggestions, and support.  ... 
doi:10.1093/ietele/e88-c.4.520 fatcat:4zj36rq45jblpjjvn3balgdcti

Dynamic voltage and frequency management for a low-power embedded microprocessor

M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, M. Shimura
2005 IEEE Journal of Solid-State Circuits  
in Personal Information Management scheduler application and 40% power reduction in MPEG4 movie playback.  ...  The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of 5 mV, achieving 82% power reduction  ...  Hagiwara for help, suggestions, and support.  ... 
doi:10.1109/jssc.2004.838021 fatcat:ksvix526mrggfogl35y37ufoei

Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2017 Japanese Journal of Applied Physics  
Takako of Focal Agency for excellent technical assistance.  ...  Part of this research was supported by the JSPS ImPACT Program, R&D for Next-Generation IT of MEXT of Japan, and JSPS KAKENHI Grant Number 16KT0187.  ...  This technique can apply LIMstyle circuitry in general and would contribute to the design of highly reliable and low-power NV-LIM LSI.  ... 
doi:10.7567/jjap.56.04cn01 fatcat:onuajm2vdfgbtikn2fvsxkuzoa

A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI

Sadayuki Yasuda, Shoko Ohteru, Yasuyuki Itoh, Koji Yamazaki, Yuusuke Sekihara, Takashi Aoki, Masami Urano, Tsugumichi Shibata
2013 IEICE Electronics Express  
A new power management scheme enables us to apply the power-gating technique to a 200-Gbps packet forwarding circuit.  ...  This technique reduces the power consumption by 14% when the total traffic rate is less than half of the maximum rate of 200 Gbps.  ...  Experimental results Conclusion We have demonstrated the first power gating technique for a 200-Gbps packet-forwarding LSI.  ... 
doi:10.1587/elex.10.20130231 fatcat:depieubobzbd5px4x5pni7uewa

LSI

S. F. Dennis, M. G. Smith
1971 Proceedings of the November 16-18, 1971, fall joint computer conference on - AFIPS '71 (Fall)  
When communications processors must be ·fast, bipolar techniques can be used for the WCS-and perhaps for their main memories as well.  ...  Again, by applying our rule-of-thumb LSI projections to LSI parts, and lesser reductions to other components, we have approximately a 3-to-1 reduction, as shown in Table III .  ... 
doi:10.1145/1478873.1478917 dblp:conf/afips/DennisS72 fatcat:sbd5pyokpre53esqfrddb7op7u

A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H±288, V:±96) motion estimation and 81-MOPS controller

E. Ogura, M. Takashima, D. Hiranaka, T. Ishikawa, Y. Yanagita, S. Suzuki, T. Fukuda, T. Ishii
1998 IEEE Journal of Solid-State Circuits  
The power consumption was reduced by using an efficient pipeline architecture and optimizing the circuitry, especially in the motion-estimation block and the data transfers for the external SDRAM.  ...  An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator.  ...  Tsunoji for their great contributions to this work. They also would like to thank G. Wei for helping to prepare this manuscript.  ... 
doi:10.1109/4.726574 fatcat:kpuaq3o3rbc6lowkvumyqeoslm

Page 1027 of IEEE Transactions on Computers Vol. 52, Issue 8 [page]

2003 IEEE Transactions on Computers  
The hardware cost results obtained by this technique are only a first order 1027 TABLE 7 Cell-Based Libraries (LSI Logic) Used in Synthesis Library name Description A 0.18-micron L-drawn (0.1 3-micron  ...  Conventional DSP processors such as the Motorola 56000 and the TMS320C5x from TI also use such a technique for one or more levels of loop nesting.  ... 

SVD BASED LATENT SEMANTIC INDEXING WITH USE OF THE GPU COMPUTATIONS

Raczyński Damian, Stanisławski Włodzimierz
2017 Zenodo  
The purpose of this article is to determine the usefulness of the Graphics Processing Unit (GPU) calculations used to implement the Latent Semantic Indexing (LSI) reduction of the TERM-BYDOCUMENT matrix  ...  For both considered environments computations were performed for double and single precision data.  ...  The LSI offers up to 30% better performance than traditional lexical techniques [8] .  ... 
doi:10.5281/zenodo.3351229 fatcat:ii2ekfasf5cphi3qajukmvc4lq

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI

Y. OOWAKI
2006 IEICE transactions on electronics  
of the target module. key words: dynamic voltage/frequency scaling, system LSI, H.264, A/V codec LSI, multimedia chip  ...  The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously.  ...  To discuss the effect of power reduction techniques, it is essential to keep fare measurement conditions.  ... 
doi:10.1093/ietele/e89-c.3.263 fatcat:ii7tsenkjffzxpiu77eqlh6xl4

A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications

K. Okamoto, T. Morie, A. Yamamoto, K. Nagano, K. Sushihara, H. Nakahira, R. Horibe, K. Aida, T. Takahashi, M. Ochiai, A. Soneda, T. Kakiage (+8 others)
2003 IEEE Journal of Solid-State Circuits  
This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications.  ...  Index Terms-Analog front end (AFE), CMOS, DVD, filter, LSI, mixed-signal technology, partial response maximum likelihood (PRML), read channel, system on a chip (SoC).  ...  Especially, low cost and low power are very important issues for LSIs in these systems.  ... 
doi:10.1109/jssc.2003.818131 fatcat:oy5fsbvfzvaffa53vjueai2p2u

Large-scale integration from the user's point of view

M. G. Smith, W. A. Notz
1967 Proceedings of the November 14-16, 1967, fall joint computer conference on - AFIPS '67 (Fall)  
INTRODUCTION The potential LSI user views LSI promise with a great deal of anticipation, but LSI' problems with some trepidation.  ...  Obviously, he, hopes for breakthroughs to relieve the strain of having t6 squeeze the last bit of cost or performance from the existing technological approaches-and of having to contend with the added  ...  Reductions are assumed due to LSI use in the logic and special memory areas, but not in main memory.  ... 
doi:10.1145/1465611.1465623 dblp:conf/afips/SmithN67 fatcat:idayt2wy55etjgvsywy7gpf4mu

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Daisuke Suzuki, Takahiro Oka, Akira Tamakoshi, Yasuhiro Takako, Takahiro Hanyu
2021 Nonlinear Theory and Its Applications IEICE  
As a typical example, a BCNN accelerator for inferring a 32 × 32 pixel MNIST dataset is designed using a 65-nm CMOS technology, and a power reduction of 94.2% compared with that for the conventional BCNN  ...  On the contrary, standby power consumption due to the leakage current is a critical issue for conventional CMOS-only-based logic LSIs.  ...  We also thank to Silicon Artist Technology Co. for the technical assistance.  ... 
doi:10.1587/nolta.12.695 fatcat:7ihnfaccqfdevoq4446hvupwva

Linear and Non-Linear Dimensional Reduction via Class Representatives for Text Classification

Dimitrios Zeimpekis, Efstratios Gallopoulos
2006 IEEE International Conference on Data Mining. Proceedings  
It is also combined with kernel techniques to enable the analysis of data for which linear techniques are insufficient.  ...  proposed as useful tools for low rank matrix approximation and cost effective alternatives to LSI.  ...  Yang for her kind help regarding thresholding and I. Antonellis for helpful discussions. Research supported in part by a University of Patras "Karatheodori" grant.  ... 
doi:10.1109/icdm.2006.98 dblp:conf/icdm/ZeimpekisG06 fatcat:hpmaa3jgxrf7tbkmc6gy3lkp6e

The impact of ASIC devices on the SEU vulnerability of space-borne computers

R. Koga, W.R. Crain, K.B. Crawford, S.J. Hansel, S.D. Pinkerton, T.K. Tsubota
1992 IEEE Transactions on Nuclear Science  
Yee (LSI), R.L. Woodruff MSI component circuits with FPGAs. If further reductions in and PJ.  ...  Penzin for their generou°F PGAs, they also tend to be a bit more difficult to program. assistance. Thanks are also due M. Sarpa and K.A.  ...  SEV Reduction and Tolerance CL One method for reducing the SEU susceptibility of ASIC --i i _E _devices is based on the fact that memory elements can be d Lcreated using many different types of bistable  ... 
doi:10.1109/23.211354 fatcat:t3zh3gunkbahjp3wbzxtu4i7ma
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