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2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Mohsenin Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors ........................... ...............................................................  ...  Kurdahi 302 A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits ................. ........................................................  ... 
doi:10.1109/tcsi.2018.2880597 fatcat:favyhhxkwvclblo34fqe3aga2m

Design tradeoffs for tiled CMP on-chip networks

James Balfour, William J. Dally
2006 Proceedings of the 20th annual international conference on Supercomputing - ICS '06  
Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency  ...  We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors.  ...  and taper patterns (similar results were obtained using adaptive routing strategies on the Torus network).  ... 
doi:10.1145/1183401.1183430 dblp:conf/ics/BalfourD06 fatcat:yynugxhzxbfj5lgssikysmgnhm

Design tradeoffs for tiled CMP on-chip networks

James Balfour, William J. Dally
2014 25th Anniversary International Conference on Supercomputing Anniversary Volume -  
Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency  ...  We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors.  ...  and taper patterns (similar results were obtained using adaptive routing strategies on the Torus network).  ... 
doi:10.1145/2591635.2667187 fatcat:mbz2ftfiobe6no5jovyvvmaf54

An onboard processor and adaptive scanning controller for the Second-Generation Precipitation Radar

M.A. Fischman, A.C. Berkun, W. Chun, E. Im, R.J. Andraka
2005 IEEE Transactions on Geoscience and Remote Sensing  
PR-2 will rely on high-performance onboard processing techniques in order to improve the observation capabilities (swath width, spatial resolution, and precision) of a low-earth orbiting rainfall radar  ...  Using field-programmable gate arrays (FPGAs), we have developed a prototype spaceborne processor and controller module that will support advanced capabilities in the PR-2 such as autotargeting of rain  ...  ACKNOWLEDGMENT The research described in this paper was performed by the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration  ... 
doi:10.1109/tgrs.2005.844670 fatcat:3yoza5dmdbe2jd5yv5o27hsopa

Focal plane generation of multi-resolution and multi-scale image representation for low-power vision applications

J. Fernández-Berni, R. Carmona-Galán, L. Carranza-González, A. Zarándy, Á. Rodríguez-Vázquez, Bjørn F. Andresen, Gabor F. Fulop, Paul R. Norton
2011 Infrared Technology and Applications XXXVII  
of Use: http://spiedl.org/terms Proc. of SPIE Vol. 8012 80120E-5 Downloaded From: http://spiedigitallibrary.org/ on 10/18/2013 Terms of Use: http://spiedl.org/terms  ...  Downloaded From: http://spiedigitallibrary.org/ on 10/18/2013 Terms of Use: http://spiedl.org/terms Proc. of SPIE Vol. 8012 80120E-3 Downloaded From: http://spiedigitallibrary.org/ on 10/18/2013 Terms  ...  On the other hand, the dynamic power consumption of a digital processor is proportional to the frequency of its clock. 1 A tradeoff arises which is quite difficult to solve for applications requiring  ... 
doi:10.1117/12.883881 fatcat:ccf2k2odrvfzxh5icp5nqua7ka

A fully digital, energy-efficient, adaptive power-supply regulator

Gu-Yeon Wei, M. Horowitz
1999 IEEE Journal of Solid-State Circuits  
Index Terms-Adaptive control, dc-dc power conversion, frequency-locked loops, power supplies.  ...  A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits.  ...  loss components (e.g., power transistor's "on" resistance) in series with the inductor are lumped together as , and is the effective parallel resistance of the load circuit and the nonideal resistance  ... 
doi:10.1109/4.753685 fatcat:lpc2gyu3mzfnxjzz6v6q26vbey

PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations

James Alfred Walker, Martin A. Trefzer, Simon J. Bale, Andy M. Tyrrell
2013 IEEE transactions on computers  
performance.  ...  This paper describes an adaptive, evolvable architecture that allows for correction and optimization of circuits directly in hardware using bioinspired techniques.  ...  The authors would like to thank Gold Standard Simulations Ltd and ngenics Ltd for the use of RandomSpice and MOTIVATED.  ... 
doi:10.1109/tc.2013.59 fatcat:df2nxtq4wvblxdhq3ool4yhyhy

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 SIGARCH Computer Architecture News  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  ., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power delivery network (PDN) that satisfies noise margins without compromising performance  ...  Trading Power Pads for Performance Our primary interest is the tradeoff between power supply pads and I/O pads.  ... 
doi:10.1145/2678373.2665728 fatcat:kkwbrdtdrjasfetcshx643vr3e

Architecture implications of pads as a scarce resource

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron
2014 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)  
In this paper, we develop a pre-RTL PDN model, VoltSpot, for the purpose of studying the performance and noise tradeoffs among power supply and I/O pad allocation, the effectiveness of noise mitigation  ...  ., C4 pads) between power supply and I/O, and the loss of such resources to electromigration, means that constructing a power delivery network (PDN) that satisfies noise margins without compromising performance  ...  Trading Power Pads for Performance Our primary interest is the tradeoff between power supply pads and I/O pads.  ... 
doi:10.1109/isca.2014.6853199 dblp:conf/isca/ZhangWMSS14 fatcat:yruivsyndbapvmp4izc3sbsc34

A Fully Integrated On-Chip DC–DC Conversion and Power Management System

G. Patounakis, Y.W. Li, K.L. Shepard
2004 IEEE Journal of Solid-State Circuits  
It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation.  ...  The use of switched-capacitor supplies offers better efficiencies than what is achievable with linear regulators alone.  ...  The use of the turbo control signal eases this tradeoff.  ... 
doi:10.1109/jssc.2003.822773 fatcat:3decsoiyt5gldaxgd65sryicom

Networks on chips: a new SoC paradigm

L. Benini, G. De Micheli
2002 Computer  
The network adapter associated with each node connects to a switch's port.  ...  Wiring pitch and width increase in higher wiring levels so that wires at top levels can be much wider and thicker than low-level wires. 5 Increased width reduces wire resistance, even considering the  ... 
doi:10.1109/2.976921 fatcat:dtau6kla4nguriihuo4xs6szsi

Power reduction techniques for microprocessor systems

Vasanth Venkatachalam, Michael Franz
2005 ACM Computing Surveys  
Power consumption is a major factor that limits the performance of computers. We survey the "state of the art" in techniques that reduce the total power consumed by a microprocessor system over time.  ...  These techniques may eventually allow computers to break through the "power wall" and achieve unprecedented levels of performance, versatility, and reliability.  ...  The decision of when to spin down an idle disk involves tradeoffs between power and performance.  ... 
doi:10.1145/1108956.1108957 fatcat:3v56rcg7yrejffkqp64hev4exi

CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis

Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt
2010 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications.  ...  Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated  ...  32 bit data bus width (4 5_32b) and 4) a 2-master, 3-slave bus matrix with 64 bit data width (2 3_64b).  ... 
doi:10.1109/tvlsi.2008.2009304 fatcat:b2t6nxn32je7ndgu6bucm24c6e

An Efficient Lightweight Cryptographic Instructions Set Extension for IoT Device Security

Wajih El Hadj Youssef, Ali Abdelli, Fethi Dridi, Rim Brahim, Mohsen Machhout, Ricardo Chaves
2022 Security and Communication Networks  
Obtained results show that our proposed concepts not only can achieve good encryption results with high performance and reduced cost but also are secure enough to resist against the most common attacks  ...  The customized ReonV RISCV processor is implemented on a Xilinx FPGA platform and is evaluated for Slice LUTs plus FF-pairs, frequency, and throughput.  ...  AES, DES, 3DES, and SHA using Cadence LX7 Processor and Xtensa platform. eir obtained results provide excellent tradeoff with the area, memory, and cycle count performances.  ... 
doi:10.1155/2022/9709601 fatcat:jwpnxxezuvg2bjeqvt233pdveq

480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition

Rafal Karakiewicz, Roman Genov, Gert Cauwenberghs
2007 IEEE Journal of Solid-State Circuits  
Index Terms-Adiabatic low-power techniques, computational memory, pattern recognition, resonant clock supply.  ...  We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load.  ...  His activities include design and development of micropower analog and mixed-signal systems-on-chips performing adaptive signal processing and pattern recognition. Dr.  ... 
doi:10.1109/jssc.2007.907224 fatcat:h65muel5vfas7fpv7rpte7eafq
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