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Automatic IP Generation of FFT/IFFT Processors with Word-Length Optimization for MIMO-OFDM Systems

Pei-Yun Tsai, Chia-Wei Chen, Meng-Yuan Huang
2010 EURASIP Journal on Advances in Signal Processing  
With the flexible architecture and the effective word-length searching techniques, we can strike a good balance for the performance and the hardware cost of the generated IP cores.  ...  The finite-precision effect in an FFT processor is first analyzed, and then an effective word-length searching algorithm is proposed and incorporated in the proposed IP generator.  ...  Acknowledgment This work was supported in part by the National Science Council, Taiwan, under Grants no. NSC 98-2220-E-008-004 and NSC 98-2220-E-008-001.  ... 
doi:10.1155/2011/136319 fatcat:goh3zmlbereoll6nqtf4j6szee

Power-Performance Optimal DSP Architectures and ASIC Implementation

Farhana Sheikh, Melinda Ler, Radu Zlatanovici, Dejan Markovic, Borivoje Nikolic
2006 2006 Fortieth Asilomar Conference on Signals, Systems and Computers  
A hierarchical, sensitivity-based ASIC design methodology is proposed and demonstrated in the implementation of power-performance optimal signal processing kernels for wireless applications.  ...  The methodology is exemplified in the selection of architecture and design of a flexible digital finite impulse response (FIR) filter.  ...  The cost of flexibility is measured as the additional power and area required to support flexibility in terms of tap programmability; and in terms of programmability of input and coefficient word length  ... 
doi:10.1109/acssc.2006.355004 fatcat:fmb6qfacdjc5vdlxb2ctnlnt3a

Configurable multiplier modules for an adaptive computing system

O. A. Pfänder, H.-J. Pfleiderer, S. W. Lachowicz
2006 Advances in Radio Science  
But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation  ...  In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated  ...  The ALUs are designed for increased flexibility in order to support variable data word-lengths for various types of computation.  ... 
doi:10.5194/ars-4-231-2006 fatcat:6go2gffrirgg5dj6amnbj65mza

Area-efficient mixed-radix variable-length FFT processor

Chen Yang, Chunpeng Wei, Yizhuang Xie, He Chen, Cuimei Ma
2017 IEICE Electronics Express  
In order to minimize the number of occupied multipliers while supporting more flexible FFT length, a 4-parallel radix-2 3 mixed radix-2/3/4 architecture is adopted.  ...  This paper presents a mixed-radix multipath delay feedback (MDF) FFT processor with variable-length.  ...  Acknowledgements This work was supported by the Chang Jiang Scholars Programme under Grant T2012122, the Hundred Leading Talent Project of Beijing Science and Technology under Grant Z141101001514005.  ... 
doi:10.1587/elex.14.20170232 fatcat:z6vv6nncczddvoed3n346ni43u

Comparison of reconfigurable structures for flexible word-length multiplication

O. A. Pfänder, R. Nopper, H.-J. Pfleiderer, S. Zhou, A. Bermak
2008 Advances in Radio Science  
Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications.  ...  But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA.  ...  The work described in this paper is supported by a grant from the Research Grant Council of Hong Kong S.A.R. and the German DAAD (Project No. G-HK019/05).  ... 
doi:10.5194/ars-6-113-2008 fatcat:a5u4pwxmbfggpm4mgwigf52z7e

Design of Multipath Delay Commutator Architecture based FFT Processor for 4th Generation Systems

Amjadha. A, E.Konguvel E.Konguvel, J.Raja J.Raja
2014 International Journal of Computer Applications  
In this paper an efficient implementation of FFT/IFFT processor for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length is presented.  ...  For area and time optimization and to reduce power consumption, the Read Only Memories (ROM"S) which is used to store twiddle factor is replaced by complex multiplier.  ...  RESULTS AND COMPARISON Code development, synthesis, analysis related to timing and power for the proposed MDC FFT PROCESSOR with variable length for OFDM are carried out in Altera and simulation is done  ... 
doi:10.5120/15683-4519 fatcat:yvv5atnqhvewddmhqvhbqzt52i

On the Implementation of Fixed-point Exponential Function for Machine Learning and Signal Processing Accelerators [article]

Mahesh Chandra
2021 arXiv   pre-print
The implementation presented here significantly reduces the number of multipliers and adders. This is further optimized using mixed world-length implementation for the series expansion.  ...  This paper presents an optimized implementation of exponential function for variable precision fixed point negative input.  ...  VARIABLE WORD-LENGTH IMPLEMENTATION (Cubic term) in rows and Ts (square term) in columns.  ... 
arXiv:2112.02263v1 fatcat:5hotqdmrtzc2nc4vsbvwgr6vz4

DESIGN OF POWER AND DELAY EFFICIENT 32 BIT X 32 BIT MULTI-PRECISION MULTIPLIER WITH OPERANDS SCHEDULER

Jitha K T .
2015 International Journal of Research in Engineering and Technology  
Experimental results show that the proposed MP Multiplier provides a 14.55% reduction in power consumption and 9.67% reduction in delay compared with conventional razor based DVS MP Multiplier.  ...  To reduce power consumption and delay, replaces the razor flip flop and voltage scaling unit .The Look up table (LUT) together with dynamic voltage and frequency management system configure the multiplier  ...  Our sincere thanks to the experts who have contributed towards the development of the paper.  ... 
doi:10.15623/ijret.2015.0402082 fatcat:5s63hf7ad5ghnnealw53wq4d5m

Word-length optimization for differentiable nonlinear systems

George A. Constantinides
2006 ACM Transactions on Design Automation of Electronic Systems  
In addition, the power-optimizing capabilities of word-length optimization are studied.  ...  Application of the proposed procedure to adaptive filters and polynomial evaluation circuits realized in a Xilinx Virtex FPGA has resulted in area reductions of up to 80% (mean 66%) combined with power  ...  ACKNOWLEDGMENTS The contributions of Mr. Abunaser Miah and Mr. Nalin Sidahao, and the guidance of Profs. Peter Y. K. Cheung and Wayne Luk are gratefully acknowledged.  ... 
doi:10.1145/1124713.1124716 fatcat:sp3qj7lzizcwpoqobrp4ttf4ii

Cross-layer resource allocation for downlink access using instantaneous fading and queue length information

Luis M. Lopez-Ramos, Antonio G. Marques, Javier Ramos, Antonio J. Caamano
2010 2010 IEEE Globecom Workshops  
Motivated by those findings, this work develops optimal algorithms that use instantaneous fading and queue length information to allocate resources at transport, link and physical layers.  ...  Our focus is on the downlink channel of a cellular system where an access point sends different information to several users through a set flatfading orthogonal channels.  ...  In other words, the developed schemes reveal the way in which the length of the queues can be used to optimize the performance of the network.  ... 
doi:10.1109/glocomw.2010.5700130 fatcat:l3fytgytgjg45nsuwiohoe7wga

DSP Code Generation with Optimized Data Word-Length Selection [chapter]

Daniel Menard, Olivier Sentieys
2004 Lecture Notes in Computer Science  
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption.  ...  Indeed, the latest DSP generation allows to manipulate a wide range of data types through sub-word parallelism and multiple-precision instructions.  ...  An operator (multiplier, adder, shifter) of word-length N is split to execute k operations in parallel on sub-word of word-length N/k.  ... 
doi:10.1007/978-3-540-30113-4_16 fatcat:o7bwbfhaejgl5lc5rxrctdu6h4

Fixed-Point Configurable Hardware Components

Romuald Rocher, Daniel Menard, Nicolas Herve, Olivier Sentieys
2006 EURASIP Journal on Embedded Systems  
In terms of arithmetic accuracy, the generated architecture can generally only be configured through the input and output word lengths.  ...  In this paper, a new kind of method to optimize fixed-point arithmetic IP has been proposed. The architecture cost is minimized under accuracy constraints defined by the user.  ...  lengths of all variables.  ... 
doi:10.1155/es/2006/23197 fatcat:7gycrr4qjfh55hkupltluplmju

Fixed-Point Configurable Hardware Components

Romuald Rocher, Daniel Menard, Nicolas Herve, Olivier Sentieys
2006 EURASIP Journal on Embedded Systems  
In terms of arithmetic accuracy, the generated architecture can generally only be configured through the input and output word lengths.  ...  In this paper, a new kind of method to optimize fixed-point arithmetic IP has been proposed. The architecture cost is minimized under accuracy constraints defined by the user.  ...  lengths of all variables.  ... 
doi:10.1186/1687-3963-2006-023197 fatcat:24my57rt2zazxad3xtlrpueq6e

High Speed Implementation of 16 & 32 Bit Multiplication in MCMA Block of Fir Filter Using Column Compression Multipliers & Hybrid Adder
English

T.S.Ghouse Basha, S.Emmanuel Steeven Singh
2014 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering  
Multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR Filters, Digital Signal Processors, and Multiprocessors.  ...  The Column Compression multipliers divide the Partial Product Summation Tree (PPST) into two parts so that the column compression can be achieved in parallel independently and reduces to a height of 2  ...  response, the sampling frequency, the word length of the input data and order of the filter.  ... 
doi:10.15662/ijareeie.2014.0309028 fatcat:mrlubli73rgyljqfj4isgixdda

Hardware speedups in long integer multiplication

M. Shand, P. Bertin, J. Vuillemin
1990 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures - SPAA '90  
First, we demonstrate how a simple hardware 512 bits integer multiplier coupled with a low end workstation host yields performance on long arithmetic superior to that of the fastest computers for which  ...  Second, we specialize this hardware in order to speed-up one specific application of long integer arithmetic, namely Rivest-Shamir-Adleman public-key cryptography [RSA].  ...  The variable-length bus multiplier is a straightforward extension of the fixed-length bus multiplier.  ... 
doi:10.1145/97444.97679 dblp:conf/spaa/ShandBV90 fatcat:5rdzgv7ozfa3fk6k5i5ugm4zca
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