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Power dissipation reductions with genetic algorithms

E. Takahashi, M. Murakawa, Y. Kasai, T. Higuchi
NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.  
Two cases of power dissipation reduction with postfabrication adjustment using genetic algorithms are introduced in this paper.  ...  The second case is the IF (Intermediate Frequency) filter analog LSI used in cellular phones, where the reduction in power dissipation is realized by circuit parameter adjustment.  ...  dissipations with Post-Fabrication Adjustment based on Genetic Algorithms (GAs).  ... 
doi:10.1109/eh.2003.1217654 dblp:conf/eh/TakahashiMKH03 fatcat:breb25zidrcmrnz6gcamw3qjuq

Low Power Realization of FIR Filters Using Optimization Techniques

Er. Neha Goyal
2012 IOSR Journal of Engineering  
Two such techniques "Steepest descent" and "Genetic Algorithm" are presented to minimize these measures of power dissipation .Experimental results on a FIR filter example show that the Genetic coefficient  ...  In this paper an algorithm for optimizing coefficients of a Finite Impulse Response (FIR) filter, so as to reduce power dissipation of its implementation on a programmable Digital Signal Processor is presented  ...  INTRODUCTION With the recent trend towards portable computing and wireless communication systems, power dissipation has become an important design consideration.  ... 
doi:10.9790/3021-02821218 fatcat:dko5w5zlurad3iic6kyib7siym

Optimization of Power Consumption in VLSI Circuit

Mr. Praveen Kumar Gupta, Jagdeep Kaliraman
2014 IOSR Journal of Electrical and Electronics Engineering  
It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit.  ...  Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power.  ...  Genetic Algorithm can reduce number of gates, which consequently reduce power consumption; as the work of Coello [2] , shows on 2-bit adder and 2-bit multiplier with a particular "cardinality" that 56%  ... 
doi:10.9790/1676-09236266 fatcat:u6uz5kctbngvfig7wisv4trmju

A Modified Algorithm for Voltage Assignment and Floorplanning of SOC Designs

B. Srinath, P. Arunapriya
2015 Indian Journal of Science and Technology  
A new genetic algorithm based optimization is proposed to give the best solution of floorplan which reduces the dynamic power.  ...  Voltage island reduction is carried over by matching algorithm.  ...  Our contribution in this paper is, A graph matching algorithm based is used for volt-• age island reduction considering timing and power dissipation.  ... 
doi:10.17485/ijst/2015/v8i35/81012 fatcat:neysj3zsxrbmlm4xcixpitjnpy

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

Uday Panwar, Kavita Khare
2014 International Journal of Computer Applications  
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap  ...  To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation Leakage power in CMOS VLSI circuits can be controlled at the circuit level.  ...  NAND2 => NAND with SLEEP transistor as a variation) 3) Check for the leakage power reduction.  ... 
doi:10.5120/17181-7276 fatcat:nc6bp3faavemnlox3uexpwq3aq

Iterative schedule optimization for voltage scalable distributed embedded systems

Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
2004 ACM Transactions on Embedded Computing Systems  
Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively.  ...  To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks.  ...  The total energy dissipation is E = 45.93µJ. This means an energy reduction of 20.5% compared to a reduction of 8.2% obtained with a power profile neglecting approach.  ... 
doi:10.1145/972627.972636 fatcat:s4vfdizfdzhennjrivmgus7mbe

Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing

W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Y. Tsai
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account.  ...  The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches.  ...  Section 2 reviews different power reduction techniques and previous works. Section 3 gives a brief introduction on genetic algorithm.  ... 
doi:10.1145/1013235.1013276 fatcat:nuvgg2bhabgitkakhrm6xqvsja

Considering power variations of DVS processing elements for energy minimisation in distributed systems

Marcus T. Schmitz, Bashir M. Al-Hashimi
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems  ...  Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system.  ...  Experimental results demonstrate that combining the proposed scaling heuristic with a genetic algorithm based design space exploration yields to substantially reduced (up to 80.7%) energy dissipations.  ... 
doi:10.1145/500001.500060 fatcat:2l5pup5f2jbbzcqljwguhkbt54

Considering power variations of DVS processing elements for energy minimisation in distributed systems

Marcus T. Schmitz, Bashir M. Al-Hashimi
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems  ...  Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system.  ...  Experimental results demonstrate that combining the proposed scaling heuristic with a genetic algorithm based design space exploration yields to substantially reduced (up to 80.7%) energy dissipations.  ... 
doi:10.1145/500058.500060 fatcat:5rhrlg34gje4bpkxu4rre35jci

BackTrack Input Vector Algorithm for Leakage Reduction in CMOS VLSI Digital Circuit Design

Uday Panwar, Kavita Khare
2014 International Journal of VLSI Design & Communication Systems  
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and  ...  This method is independent of process technology and does not require any additional power supply.  ...  In [9] , a genetic algorithm was recommended to overawe the problem of MLV Genetic algorithm has an exponential solution space concerning the number of primary inputs.  ... 
doi:10.5121/vlsic.2014.5201 fatcat:a3k22hrnova7lcunpncvuyu64q

Low Power, High Speed MUX Based Area Efficient Dadda Multiplier [chapter]

Kalaiyarasi.D, Pritha.N, Srividhya.G, Padmapriya.D
2021 Advances in Parallel Computing  
In this paper, a 4-bit multiplier is constructed using the Dadda algorithm with enhanced Full and Half adder blocks to achieve a smaller size, lower power consumption, and minimum propagation delay.  ...  In the second phase, each stage of the Dadda tree algorithm is built with an enhanced Full and half adders to reduce the design area, propagation delay, and power consumption while still meeting the requirements  ...  The digital design with low power dissipation and minimal delay, as well as maximum throughput and high speed can be achieved byvarious techniques such as merged delay transformation [6] , genetic algorithm  ... 
doi:10.3233/apc210087 fatcat:nnlnx4s4anhmdhyhd6gfca6iqe

Thermal-aware task mapping for communication energy minimization on 3D NoC

Lili Shen, Ning Wu, Gaizhen Yan, Fen Ge
2017 IEICE Electronics Express  
Moreover, our proposed algorithm achieves up to 63.34% communication energy consumption reduction.  ...  However, due to its high power density and strong vertical thermal correlation, thermal issues in 3D NoC are critical.  ...  Experimental results show that, compared with other thermal-aware task mapping algorithms, the propose algorithm can achieve up to 63.34% reduction in communication energy consumption and up to 5.75K reduction  ... 
doi:10.1587/elex.14.20170900 fatcat:k3ifqyx3inaj7jb5ekzcpd3ydi

Strategies and Techniques for Optimizing Power in BIST: A Review

Amandeep Singh, P. Mohan Kumar, Mohinder Bassi
2014 International Journal of Computer Applications  
Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation.  ...  Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to  ...  Genetic algorithm is used in [3] to locate the vectors to be inserted in LFSR.  ... 
doi:10.5120/14976-3175 fatcat:pg7rprxbmngghg477zkegneh6e

Minimizing the Head Losses Increases Caused by Valves in Hydraulic Networks

V.E.M.G. Diniz, Jean Revolta, Bruno Pinheiro, Rozangela Souza, Podalyro Amaral Souza, Edevar Luvizotto Junior
2015 Social Science Research Network  
The hybrid model uses a genetic algorithm to minimize the dissipated hydraulic power sum in the whole hydraulic network for all calculation time steps of the extended period simulation (objective function  ...  It's concluded that the dissipated power minimization was an effective way to optimize the studied hydraulic network operations by minimizing the head losses increases caused by the installed valves.  ...  The results of the second output file represent the hydraulic network with the minimum dissipated hydraulic power sum.  ... 
doi:10.2139/ssrn.2634112 fatcat:cq262kkjf5gthhk24hyfvvyoky

Genetic Algorithm For Leakage Reduction Through Ivc Using Verilog

S.Meera
2018 Zenodo  
GENETIC ALGORITHM FOR LEAKAGE REDUCTION THROUGH IVC USING VERILOG VLSI design constraints are always area, power and delay.  ...  Power consumption of VLSI has become a leading design concern with the growth of complexity and density.  ...  It is also reduces the runtime with leakage power reduction. The paper is organized as follows.  ... 
doi:10.5281/zenodo.1237451 fatcat:a7ahhxuvr5a67ny77bxb3ev2xi
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