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Comparative Analysis of Polynomial FIR Multirate DSP Applications

S. Arunkumar, P. Ganesh Kumar
2012 International Journal of Computer Applications  
Zero stuffing is performed in the process of interpolating a discrete-time signal, and then low-pass filtering the resulting signal.The proposed decimator is implemented using MATLAB as standard FIR, Half  ...  Multirate DSP systems in which different parts at different sampling rates. The icrease in the sampling interval results in more time availble for processing.  ...  , the synthesis and the hardware implementation of a decimation filter designed for 6-bit data stream input, from a fourth-order sigmadelta modulator adapted for multistandard wireless receiver.  ... 
doi:10.5120/7421-0155 fatcat:m7aeab5uazaopovolisgdztwc4

Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers

P.K. Prakasam, M. Kulkarni, Xi Chen, Zhuizhuan Yu, S. Hoyos, J. Silva-Martinez, E. Sanchez-Sinencio
2008 IEEE Transactions on Circuits and Systems - II - Express Briefs  
Index Terms-Cognitive radio (CR), frequency-domain (FD) receiver, multistandard receiver, software-defined radio, transformdomain (TD) receiver.  ...  The flexibility and scalability of TD receivers allow for the design of receivers that can cope with a large range of narrow-band and broad-band communications standards.  ...  Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon.  ... 
doi:10.1109/tcsii.2008.919480 fatcat:xrm5tyzqnvha7c7nudtkqdctei

Polynomial based Design of CIC Compensation Filter used in Software Defined Radio for Multirate Signal Processing

Richa Richa, R. K. Singh
2012 International Journal of Computer Applications  
This paper presents a simple design of compensation FIR filter for CIC decimation filter which will correct the passband droop.  ...  DDC use CIC decimation filters for sample rate decimation. CIC decimation filters require less computation but large passband droop occurs in the frequency response.  ...  This concept has been developed for the first stage of the decimation chain of a multistandard radio receiver previously also [3]- [6] .  ... 
doi:10.5120/4909-7436 fatcat:pkvzskbrunhorgjw2iaqmqjcui

A reconfigurable RF sampling receiver for multistandard applications

Anis Latiri, Loïc Joet, Patricia Desgreys, Patrick Loumeau
2006 Comptes rendus. Physique  
decimation and lowpass filtering.  ...  These techniques are based on direct RF sampling and discrete-time analog signal processing and allow for a great flexibility and reduction of cost and power consumption in a reconfigurable design environment  ...  In addition to offering an improved alias rejection, the proposed filter does not result in power consumption increase and is above all adapted for multi-standard receiver operations.  ... 
doi:10.1016/j.crhy.2006.07.007 fatcat:7vezilw4rjfhdnemgxjmmounbi

A new interpolation technique for time interleaved $$\Upsigma\Updelta$$ A/D converters

Ali Beydoun, Chadi Jabbour, Van-Tam Nguyen, Patrick Loumeau
2011 Analog Integrated Circuits and Signal Processing  
Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers.  ...  The proposed technique was simulated and implemented in a four channel time interleaved sigma-delta designed in a 1.2 V 65 nm CMOS process.  ...  Acknowledgements This research work was supported by the French Research Agency in the frame of project Versanum ANR-05-RNRT-010-01.  ... 
doi:10.1007/s10470-011-9721-7 fatcat:7c2hb3gnhraifhcjgaleg2z7i4

Software-defined radio receiver: dream to reality

R. Bagheri, A. Mirzaei, M.E. Heidari, S. Chehrazi, Minjae Lee, M. Mikhemar, W.K. Tang, A.A. Abidi
2006 IEEE Communications Magazine  
This article describes a fully integrated 90 nm CMOS software-defined radio receiver operating in the 800 MHz to 5 GHz band.  ...  Unlike the classical SDR paradigm, which digitizes the whole spectrum uniformly, this receiver acts as a signal conditioner for the analog-to-digital converters, emphasizing only the wanted channel.  ...  Meanwhile, the power consumption should be reasonably low for portable applications.  ... 
doi:10.1109/mcom.2006.1678118 fatcat:audkvfmdlfdtnnpox46e5goyim

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs
2017 International Journal of Reconfigurable Computing  
We intend to take this DSL and supporting framework further to provide a rapid prototyping system for SDR application development to programmers not experienced in HDL coding.  ...  Finally, we propose our design for a Domain-Specific Language (DSL) and supporting tool-flow, which we are in the process of building using our SDR library and the Delite DSL framework.  ...  Acknowledgments The authors sincerely thank SKA for funding this project and members of the SDRG and RRSG groups at UCT for their support and advice.  ... 
doi:10.1155/2017/3925961 fatcat:5hj7giryl5ex7kfpu37zcuomti

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

R. Mahesh, A. P. Vinod, Edmund M-K. Lai, Amos Omondi
2009 Journal of Signal Processing Systems  
This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers.  ...  The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task.  ...  The channelizers in SDR receivers must be realized to meet the stringent specifications of low power consumption and high speed [3, 4] .  ... 
doi:10.1007/s11265-008-0327-y fatcat:mcyuxew6cvhwpbrxxz7km6pegy

Design considerations and implementation of a DSP-based car-radio IF Processor

M. Sala, F. Salidu, F. Stefani, C. Kutschenreiter, A. Baschirotto
2004 IEEE Journal of Solid-State Circuits  
The described chip, realized in a 0.18-m CMOS technology, occupies an area of 15.2 mm 2 and is enclosed in a 64-pin package.  ...  This paper describes design considerations and the implementation of a software defined radio receiver encompassing intermediate frequency (IF) digitization.  ...  The authors wish to thank all of them, in particular, P. Ruffino for program management, G. Boarin, P. Kirchlechner, and G.  ... 
doi:10.1109/jssc.2004.829402 fatcat:hxywbljzerhdlik7fjpv4kouii

A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

ZhongYuan Hou, Fan Yang, JunHua Liu, Xing Zhang
2014 Science China Information Sciences  
A power efficient 1.0625-3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications.  ...  The proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter, and a passive equalizer that achieves 4 dB transmission in the receiver.  ...  The proposed power-efficient SST TX driver uses a 3bit 2-tap FIR filter to compensate for high frequency losses of up to 6 dB at 3.125 Gb/s.  ... 
doi:10.1007/s11432-013-4949-8 fatcat:vqnu4b2ndbbkjgr56v7scdrz5y

A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode $\Delta\Sigma$ Receiver

Charles Wu, Elad Alon, Borivoje Nikolic
2014 IEEE Journal of Solid-State Circuits  
A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS.  ...  For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range.  ...  In particular, the authors would like to thank A. Niknejad, D. Allstot, C. Hull, H. Khorramabadi, M. Reiha, K. Nishimura, L. Kong, and J. C. Chien for discussion and support.  ... 
doi:10.1109/jssc.2014.2319249 fatcat:gnvawn5p7fbm3csnpzje4ntqwu

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

Yo-Chuol Ho, Robert Bogdan Staszewski, Khurram Muhammad, Chih-Ming Hung, Dirk Leipold, Kenneth Maggio
2006 EURASIP Journal on Wireless Communications and Networking  
A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers.  ...  We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology.  ...  The two FIR filters do not have appreciable filtering capability at low frequencies and are mainly used for antialiasing.  ... 
doi:10.1155/wcn/2006/62905 fatcat:x4r73eirsjakzerkc3vfqnx6ca

A Rapid Prototyping Environment for Wireless Communication Embedded Systems

Bryan A. Jones, Joseph R. Cavallaro
2003 EURASIP Journal on Advances in Signal Processing  
The paper proves that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.  ...  Key technologies required to meet this challenge include new types of programmable components that offer novel trade-offs between flexibility and efficiency, models for exchange of intellectual property  ...  In addition, we would like to thank Xilinx for donating the FPGA chips and the software tools.  ... 
doi:10.1155/s111086570330304x fatcat:3ird7hyyzjeb5bmrqa6ztx7574

FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER

P Devi, R Bhuvaneshwaran
2014 unpublished
Coefficient decimated polyphase FIR filter bank structure implemented for receiving narrow band channels effectively in multistandard environment.  ...  Coefficient decimation (CD) based filter bank can offer a good trade-off between reconfigurability and low complexity which satisfy most of the requirements for SDR receivers.  ...  The amount of computation and the corresponding power consumption of filter are directly proportional to the filter order. First, design an N-tap low pass FIR filter as the modal filter.  ... 
fatcat:7guigfymxjg4nn5nrpe2j3ubeq

Embedding Mixed-Signal Design in Systems-on-Chip

J.M. Rabaey, F. De Bernardinis, A.M. Niknejad, B. Nikolic, A. Sangiovanni-Vincentelli
2006 Proceedings of the IEEE  
Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.  ...  We present some of these solutions, including a structured platform-based design methodology to enable a meaningful exploration of the broad design space and to classify potential solutions in terms of  ...  authors wish to acknowledge the contributions of the students and sponsors of the Berkeley Wireless Research center, as well as the SRC and the SIA MARCO centers (GSRC and C2S2) to the topics discussed in  ... 
doi:10.1109/jproc.2006.873609 fatcat:bfsn4niuozbtzmyccioarvqyuq
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