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Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application

A. Lambrechts, P. Raghavan, A. Leroy, G. Talavera, T.V. Aa, M. Jayapala, F. Catthoor, D. Verkest, G. Deconinck, H. Corporaal, F. Robert, J. Carrabina
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)  
This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from  ...  We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks.  ...  Driver application and context The power breakdown for an NoC platform is measured for a representative application consists of a video chain typically used in digital cameras (Fig. 1 ).  ... 
doi:10.1109/asap.2005.52 dblp:conf/asap/LambrechtsRLTAJCVDCRC05 fatcat:ref5srxb6jdlvohxijff5d32si

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Jeong-Ho Woo, Hoi-Jun Yoo
2013 IEEE Journal of Solid-State Circuits  
A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams.  ...  The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy.  ...  However, their achievable computing power within limited power budget of mobile platforms is still insufficient for HD video-based object recognition, one of the most complex vision applications.  ... 
doi:10.1109/jssc.2012.2220651 fatcat:uh4ec3i64vdmjdev5sgck7iv2i

FARSI: Facebook AR System Investigator for Agile Domain-Specific System-on-Chip Exploration [article]

Behzad Boroujerdian, Ying Jing, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi
2022 arXiv   pre-print
., for Network-on-a-Chip subsystem)  ...  Domain-specific SoCs (DSSoCs) are attractive solutions for domains with stringent power/performance/area constraints; however, they suffer from two fundamental complexities.  ...  FARSI is an open-source project and it has been evaluated at a major industry organization for industry-relevant use cases that require DSSoC solutions in a highly resource-constrained environment such  ... 
arXiv:2201.05232v2 fatcat:yrs7k4tgszfpziy6t7wghhywm4

On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems

Wonje Choi, Karthi Duraisamy, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
2018 IEEE transactions on computers  
platforms running the above-mentioned CNN training workloads.  ...  The proposed NoC achieves 1.8x reduction in network latency and improves the network throughput by a factor of 2.2 for training CNNs, when compared to a highly-optimized wireline mesh NoC.  ...  In this section, the main problem we examine is the optimization of the NoC link placement in CPU-GPU heterogeneous platforms that run deep learning applications.  ... 
doi:10.1109/tc.2017.2777863 fatcat:actbfs64dbgsdct3tr4ubfqfjq

FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity

Behzad Boroujerdian, Ying Jing, Devashree Tripathy, Amit Kumar, Lavanya Subramanian, Luke Yen, Vincent Lee, Vivek Venkatesan, Amit Jindal, Robert Shearer, Vijay Janapa Reddi
2022 ACM Transactions on Embedded Computing Systems  
., for Network-on-a-Chip subsystem), respectively. PS: This paper targets the Special Issue on Domain-Specific System-on-Chip Architectures and Run-Time Management Techniques.  ...  Domain-specific SoCs (DSSoCs) are an attractive solution for domains with extremely stringent power, performance, and area constraints. However, DSSoCs suffer from two fundamental complexities.  ...  example, in a distributed chip network within a car.  ... 
doi:10.1145/3544016 fatcat:3mb2pnifevb5jh4hmr24j2g3kq

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Hoi-Jun Yoo
2009 IEEE transactions on circuits and systems for video technology (Print)  
In this paper, a configurable heterogeneous multicore architecture with a dual-mode linear processor array and a cellular neural network on the networkon-chip platform is presented for real-time object  ...  The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively  ...  The power consumption is less than 600 mW at 1.2-V power supply while object recognition application is running at 22 frames/s on the QVGA (320 × 240) image.  ... 
doi:10.1109/tcsvt.2009.2031516 fatcat:oczezwycrrdr5frnus2gfgtb3e

A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine

Kwanho Kim, Seungjin Lee, Joo-Young Kim, Minsu Kim, Hoi-Jun Yoo
2009 IEEE Journal of Solid-State Circuits  
A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm.  ...  The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth.  ...  The power consumption is about 583 mW at 1.2 V power supply while object recognition application program is running at 22 frames/sec. Table II shows the power breakdown of the chip.  ... 
doi:10.1109/jssc.2008.2007157 fatcat:gwd33zf6ejcpbo33y43rctfp54

QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors

Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu
2010 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip  
Using a wide set of real application traces, we demonstrate the need for a multi-fractal approach and analyze various packet arrival properties accordingly.  ...  This paper identifies non-stationary effects in grid like Network-on-Chip (NoC) traffic and proposes QuaLe, a novel statistical physics-inspired model, that can account for non-stationarity observed in  ...  Figure 3 . 3 Power spectrum of inter-arrival times of data packets for different applications running on a 10×10 NoC with various L1 cache sizes: 400.perlbench for three different packet sizes: 1 flit  ... 
doi:10.1109/nocs.2010.34 dblp:conf/nocs/BogdanKMM10 fatcat:6tet5z3n65f4jjizdbtsqjtzba

Network-on-chip architectures and design methods

L. Benini, D. Bertozzi
2005 IEE Proceedings - Computers and digital Techniques  
In the long run, more aggressive solutions are needed to overcome the scalability limitation, and networks-on-chip (NoCs) are currently viewed as a 'revolutionary' approach to provide a scalable, high  ...  performance and robust infrastructure for on-chip communication.  ...  Acknowledgments The authors acknowledge the contribution of a large group of coworkers which has made it possible to write this work.  ... 
doi:10.1049/ip-cdt:20045100 fatcat:y4mpq4dhvfe7tk3t4chf5j7se4

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Emmannuel Ofori-Attah, Xiaohang Wang, Michael Agyeman
2018 EAI Endorsed Transactions on Industrial Networks and Intelligent Systems  
Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power.  ...  We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components.  ...  [20] propose a dynamic power management with a multi-objective approach for NoC based dark-silicon many-core platforms.  ... 
doi:10.4108/eai.19-9-2018.155569 fatcat:otkr6wfvkzbypdi7ihcvhoy6su

A Methodology for Constraint-Driven Synthesis of On-Chip Communications

A. Pinto, L.P. Carloni, A.L. Sangiovanni-Vincentelli
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a target library.  ...  Models for functionality, cost, and performance of each element are captured in the library together with their composition rules.  ...  COSI is a public-domain design framework for the analysis and synthesis of interconnection networks [15] .  ... 
doi:10.1109/tcad.2009.2013273 fatcat:woehsrt3lvezdgcil6ddaopiuy

Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper

Siva Satyendra Sahoo, Behnaz Ranjbar, Akash Kumar
2021 Journal of Low Power Electronics and Applications  
As a result, in addition to providing high parallelism, such hardware platforms have introduced increasing unreliability into the system.  ...  With the advancement of technology scaling, multi/many-core platforms are getting more attention in embedded systems due to the ever-increasing performance requirements and power efficiency.  ...  Application/Tasks' Criticality In general, all tasks running on a common platform, may not be equally critical (i.e., not uniform criticality) for doing a correct service.  ... 
doi:10.3390/jlpea11010007 fatcat:uvzwnfrprne7lbd2fg2goh3v2q

High Performance Network-on-Chips (NoCs) Design: Performance Modeling, Routing Algorithm and Architecture Optimization [article]

Zhiliang Qian
2014 arXiv   pre-print
For avoiding temperature hotspots, a thermal-aware routing algorithm is proposed to achieve an even temperature profile for application-specific Network-on-chips (NoCs).  ...  For this purpose, we propose a machine learning based latency regression model to evaluate the NoC designs with respect to different configurations.  ...  to implement a FPGA-based prototype and carry out a thorough comparison and analysis on the power, area overhead. 4) More applications based on the proposed NoC platform: In future, we also expect to  ... 
arXiv:1406.3790v1 fatcat:rtr5v3ptu5f37eh3wwxfjusoom

CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition

Ravi Iyer, Sadagopan Srinivasan, Omesh Tickoo, Zhen Fang, Rameshkumar Illikkal, Steven Zhang, Vineet Chadha, Paul Stillwell, Seung Eun Lee
2011 IEEE Micro  
processor running at 3 GHz) and a netbook platform with small-core microprocessors (Intel's Atom core running at 1.6 GHz).  ...  On the basis of these characteristics, we explore a recognition server design (CogniServe) that employs a heterogeneous architecture with the following key features: several small cores for low power and  ... 
doi:10.1109/mm.2011.37 fatcat:u7v3plqe2jhw3htlxbh7qdltay

Performance characterization and acceleration of Optical Character Recognition on handheld platforms

Sadagopan Srinivasan, Li Zhao, Lin Sun, Zhen Fang, Peng Li, Tao Wang, Ravishankar Iyer, Ramesh Illikkal, Dong Liu
2010 IEEE International Symposium on Workload Characterization (IISWC'10)  
processor running at 3 GHz) and a netbook platform with small-core microprocessors (Intel's Atom core running at 1.6 GHz).  ...  On the basis of these characteristics, we explore a recognition server design (CogniServe) that employs a heterogeneous architecture with the following key features: several small cores for low power and  ... 
doi:10.1109/iiswc.2010.5648852 dblp:conf/iiswc/SrinivasanZSFLWIL10 fatcat:yh3p7sugjzbkbdbm6yg7y5v3yu
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