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Past and present (and future) of parallel and distributed computation in (constraint) logic programming

FERDINANDO FIORETTO, ENRICO PONTELLI
2018 Theory and Practice of Logic Programming  
The potential for transparent exploitation of parallelism in logic programming emerged almost immediately with the birth of the paradigm (Pollard 1981).  ...  Declarative languages offer unprecedented opportunities for the use of parallelism to speed up execution.  ...  The potential for transparent exploitation of parallelism in logic programming emerged almost immediately with the birth of the paradigm (Pollard 1981 ).  ... 
doi:10.1017/s1471068418000406 fatcat:fzevnnrn5bg6pmevaykleqkxxi

Synthetic gene networks as potential flexible parallel logic gates

Hiroyasu Ando, Sudeshna Sinha, Remo Storni, Kazuyuki Aihara
2011 Europhysics letters  
This indicates the flexible parallel processing potential of this biological system.  ...  We show how a synthetic gene network can function, in an optimal window of noise, as a robust logic gate. Interestingly, noise enhances the reliability of the logic operation.  ...  Thus, the different potential well locations realize different pairs of logic truth tables in parallel.  ... 
doi:10.1209/0295-5075/93/50001 fatcat:nbx6qqsu7rgw7joyfm3drrdqii

Ultra-low-energy non-volatile straintronic computing using single multiferroic composites

Kuntal Roy
2013 Applied Physics Letters  
dynamics in the presence of room-temperature thermal fluctuations.  ...  The primary impediment to continued downscaling of traditional charge-based electronic devices in accordance with Moore's law is the excessive energy dissipation that takes place in the device during switching  ...  FIG. 3 . 3 Operations of straintronic universal logic gates. MR is low (L) [high (H)] depending on the parallel [anti-parallel] orientation of the magnetizations in the layers M1 and M2.  ... 
doi:10.1063/1.4826688 fatcat:3jwlomjtdzb7jerrs2kmligqsm

Low Complexity Out-of-Order Issue Logic Using Static Circuits

Siddhesh S. Mhambrey, Satendra K. Maurya, Lawrence T. Clark
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Background Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously.  ...  By splitting the ready signals into groups and processing them in parallel, the complexity of issuing multiple instructions is reduced.  ...  By splitting the ready signals into groups and processing them in parallel, the complexity of issuing multiple instructions is reduced.  ... 
doi:10.1109/tvlsi.2012.2184310 fatcat:2ws5o2y4ivbandtmyagvnqgwfm

Page 19 of Journal of Research and Practice in Information Technology Vol. 20, Issue 1 [page]

1988 Journal of Research and Practice in Information Technology  
Introduction PROLOG is now considered as an attractive logic programming language with its high potential for parallel execution.  ...  Since the input/output relationships of arguments are not fixed in such programs, run-time support to exploit the AND-parallelism of logic programs in a dataflow model requires control of the dynamic token  ... 

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

S.K. Karandikar, S.S. Sapatnekar
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI).  ...  SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit.  ...  A drawback of this approach is the cost requirement of duplicating logic for each finger of a potentially wide parallel stack. 4) The stack of transistors in a gate may be reordered to reduce its susceptibility  ... 
doi:10.1109/tvlsi.2003.817137 fatcat:kebxdia25fbxflyah5mewuni54

About Parallel Programming: Paradigms, Parallel Execution and Collaborative Systems

Loredana MOCEAN, Monica CEACA
2009 Informatică economică  
In the last years, there were made efforts for delineation of a stabile and unitary frame, where the problems of logical parallel processing must find solutions at least at the level of imperative languages  ...  We propose an overview in parallel programming, parallel execution and collaborative systems.  ...  Parallel execution in logical programming languages Logical programming offers clear opportunities for the implicit exploitation of parallelism.  ... 
doaj:1602054f92c748efb7d142f635002385 fatcat:7n353tnlivaozbjr6nqsy6ht3y

n-bit Data Parallel Spin Wave Logic Gate

Abdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2020 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate.  ...  To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation.  ...  III. n-BIT DATA PARALLEL SW LOGIC GATE The proposed m-input n-bit data parallel SW logic gate structure is depicted in Figure 1 .  ... 
doi:10.23919/date48585.2020.9116368 dblp:conf/date/MahmoudVCACH20 fatcat:aazplk7ucjahdci55ciwrlojhi

Page 512 of Automation and Remote Control Vol. 25, Issue 4 [page]

1964 Automation and Remote Control  
is calculated for full collector potential and full load current, In the absence of any circuit faults the transistors oper- ate under lower voltage and current loads, Thus when both parallel branches  ...  of semiconductor "NOR" elements (inverters), which are widely used in various logical control systems [2].  ... 

Guest Editors' Introduction: High-Performance Reconfigurable Computing

Duncan Buell, Tarek El-Ghazawi, Kris Gaj, Volodymyr Kindratenko
2007 Computer  
in the past few years. 4 These synergistic systems have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism through direct hardware execution  ...  This reflects a clear belief that HPRCs High-performance reconfigurable computers have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism  ...  community in the past few years. 4 These synergistic systems have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism through direct hardware  ... 
doi:10.1109/mc.2007.91 fatcat:jkzmltwyp5gy5ajn4yewgz5txe

Making Memristive Processing-in-Memory Reliable [article]

Orian Leitersdorf, Ronny Ronen, Shahar Kvatinsky
2021 arXiv   pre-print
The mMPU expands fundamental stateful logic techniques, such as IMPLY, MAGIC and FELIX, to high-throughput parallel logic and arithmetic operations within the memory.  ...  We detail ECC techniques that are based on the unique properties of the mMPU to efficiently utilize the massive parallelism.  ...  Therefore, highthroughput ECC is only supported in the naive solution for some of the potential logic and arithmetic operations.  ... 
arXiv:2109.09687v1 fatcat:tvnwbyk3yjaivngczxcesz5csm

SMAFTI packaging technology for new interconnect hierarchy

Y. Kurita, N. Motohashi, S. Matsui, K. Soejima, S. Amakawa, K. Masu, M. Kawano
2009 2009 IEEE International Interconnect Technology Conference  
We implemented a new die bonding process and the multilayer interconnect technology to form over a thousand parallel interconnects between memory and logic dies.  ...  We have developed a 3-D packaging technology called SMAFTI (SMArt chip connection with FeedThrough Interposer), which enables the implementation of a new memory/logic-interconnect hierarchy.  ...  Ito of Tokyo Institute of Technology for their helpful discussions and suggestions in planning the high-frequency characterization of interlaminar horizontal wiring.  ... 
doi:10.1109/iitc.2009.5090393 fatcat:sorjaltikzcfll3m3szqj2i2p4

Computing with spins: from classical to quantum computing

S. Bandyopadhyay
2005 Superlattices and Microstructures  
In classical computing schemes, a binary bit is represented by the spin polarization of a single electron confined in a quantum dot.  ...  If a weak magnetic field is present, the spin orientation becomes a binary variable which can encode logic 0 and logic 1. Coherent superposition of these two polarizations represent a qubit.  ...  In this case, logic 1 is preferred as the output since the all other things being equal, a spin would prefer to line up parallel to the magnetic field, rather than anti-parallel.  ... 
doi:10.1016/j.spmi.2004.09.043 fatcat:tsx54adqp5cv3a47yg364lyaom

Visualizing massively multithreaded applications with ThreadScope

Kyle B. Wheeler, Douglas Thain
2010 Concurrency and Computation  
Read and write edges come in a further two varieties, to distinguish atomic or synchronous operations from potentially unsafe operations.  ...  It also uses graph-based analysis to identify potential problems.  ...  ACKNOWLEDGEMENTS Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under  ... 
doi:10.1002/cpe.1469 fatcat:455imdfpybdh7csxm5qr6ae3yy

Parallel performance evaluation through critical path analysis [chapter]

Benno J. Overeinder, Peter M. A. Sloot
1995 Lecture Notes in Computer Science  
bounds on the potential parallelism, known as the average parallelism, a complement to the speedup and efficiency.  ...  In this paper we discuss the concept of space-time diagrams as a representation of the execution of an application, and then give a method, based on critical path analysis, for calculating nontrivial upper  ...  Notwithstanding the importance of these two measures, they do not reveal how well the potential parallelism in the application is exploited.  ... 
doi:10.1007/bfb0046692 fatcat:eacvc73obvdtfdcpwbzi7obhyu
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