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Post-placement voltage island generation for timing-speculative circuits
2013
Proceedings of the 50th Annual Design Automation Conference on - DAC '13
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Different from conventional voltage island generation techniques that work in a conservative manner to guarantee "always correct" computation, in this work, we investigate the MSV design problem for timingspeculative ...
Region-based multi-supply voltage (MSV) design, by which circuits are partitioned into multiple "voltage islands" and each island operates at a supply voltage that meets its own performance requirement ...
In this work, we formulate the MSV design problem for timing-speculative circuits, and propose a novel DP-based algorithm to generate voltage islands. ...
doi:10.1145/2463209.2488872
dblp:conf/dac/YeYSJX13
fatcat:wvqfobq26zfg5fww2mvpyg6u3i
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
2006
2006 International Conference on Field Programmable Logic and Applications
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First, we obtain the variation map for each chip by synthesizing the test circuits for each chip as a preprocessing step before detailed placement. ...
Our experimental results show that, compared to the existing FPGA placement, variation aware chipwise placement improves circuit performance by up to 19.3% for the tested variation maps. ...
For a given set of FPGA chips, we first generate the variation map for each chip, which may be obtained by synthesizing test circuits for each chip. ...
doi:10.1109/fpl.2006.311193
dblp:conf/fpl/ChengXHH06
fatcat:n5fl5repuvhepcasr7vc6jka4u
A Low-Power Integrated x86–64 and Graphics Processor for Mobile Computing Devices
2012
IEEE Journal of Solid-State Circuits
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The WAKE/RUN timing is programmable, allowing for post-silicon tuning of the delays in enabling the grid. ...
Fig. 8 . 8 Frequency vs. voltage for a representative GFX (SVT) path.
Fig. 9 . 9 SOC statistics.
Fig. 10 . 10 Transistor threshold voltage mix.
Fig. 11 . 11 DFS clock generation. ...
He then joined IBM working on logic synthesis, circuit design tools, and performance modeling for the POWER series of microprocessors. ...
doi:10.1109/jssc.2011.2167776
fatcat:c7lyh6gemfbenokg5ybdnt47la
Lithography-induced limits to scaling of design quality
2014
Design-Process-Technology Co-optimization for Manufacturability VIII
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The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore's Law scaling of layout densities, the "realizable" scaling in competitive products has for some years ...
Certain impacts seem obvious, e.g., loss of 2D flexibility and new line-end placement constraints with SADP, or algorithmically intractable layout stitching and mask coloring formulations with LELELE. ...
One popular hardware-based scheme for recovery-driven design, i.e., error detection and correction, is circuit-level timing speculation. 6, 30 Circuit-level timing speculation-based techniques detect ...
doi:10.1117/12.2047391
fatcat:tkrx334sdjcvvgsvttejeuveqa
Circuits and architectures for field programmable gate array with configurable supply voltage
2005
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused ...
circuit elements can be power-gated. ...
The BC-netlist generator takes placement and routing results by VPR [19] and generates the Basic Circuit netlist (BC-netlist) annotated with post-layout capacitance and delay. ...
doi:10.1109/tvlsi.2005.857180
fatcat:zpjhtfstb5d7fjnoakanby7dwq
Design, layout and verification of an FPGA using automated tools
2005
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05
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Our aim is to demonstrate the feasibility of a CAD flow that uses an input FPGA architecture description to generate a layout that can be sent for fabrication. ...
Simplifying and shortening the design process would be advantageous since it could reduce the time to market for new FPGAs while also enhancing architecture explorations. ...
Finally, we would like to thank NSERC and Altera for their generous funding of this project. ...
doi:10.1145/1046192.1046220
dblp:conf/fpga/KuonER05
fatcat:w6mpfglfbng4tdnj5ckhuvpxiq
Synchrophasor Measurement Technology in Power Systems: Panorama and State-of-the-Art
2014
IEEE Access
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adaptation of such devices and technologies has led the researchers to investigate multitude of challenges and pursue opportunities in synchrophasor measurement technology, PMU structural design, PMU placement ...
PMU phase angle measurements and frequency estimations are of great values for timely detection of islanding events [325] , [326] . ...
A method was devised for detection and location of generator trips based on generator rotor angle measurements obtained using PMU data [324] . ...
doi:10.1109/access.2015.2389659
fatcat:7jzjudyg6neyvoathkvugmh5a4
NanoFabrics
2001
SIGARCH Computer Architecture News
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We develop a layered abstract architecture for CAEN-based computing devices and we present preliminary results which indicate that such devices will be competitive with CMOS circuits. ...
The authors wish to thank the many reviewers for their helpful comments. ...
Predicated execution, speculative execution and code duplication (for better placement locality) would reduce the cost of control flow transfers. ...
doi:10.1145/384285.379262
fatcat:e6evgi6ibjhdhb3ucvfewopi4a
Imaging Voltage in Complete Neuronal Networks Within Patterned Microislands Reveals Preferential Wiring of Excitatory Hippocampal Neurons
2021
Frontiers in Neuroscience
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Voltage imaging with fluorescent dyes affords the opportunity to map neuronal activity in both time and space. ...
Here, we combine voltage imaging, post hoc immunocytochemistry, and patterned microisland hippocampal culture to provide imaging of complete neuronal ensembles. ...
The location of imaged islands within the 4 × 8 microisland grid was noted to aid reloaction following post hoc immunocytochemistry. ...
doi:10.3389/fnins.2021.643868
pmid:34054406
pmcid:PMC8155642
fatcat:lme3zgqm7rao7li6cxdpkljalm
Radio Frequency Reflectometry of Single-Electron Box Arrays for Nanoscale Voltage Sensing Applications
2020
Applied Sciences
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The main reason for that is that unlike a SET where the gate voltage controls conductance between the source and the drain, an SEB is a two terminal device that requires either an integrated SET amplifier ...
The experiment shows that the lack of a path for a DC current makes SEBs and DCD SETs highly electrostatic discharge (ESD) tolerant, a very desirable feature for applications. ...
Acknowledgments: The author are thankful to Anwesha Palit for reading the manuscript and making multiple suggestions.
Conflicts of Interest: The authors declare no conflict of interest. ...
doi:10.3390/app10248797
fatcat:mhnaxdacpfcghhowct5pqz6yfu
Nanoscale CMOS
1999
Proceedings of the IEEE
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Finally, we speculate on the future of CMOS for the coming 15-20 years. in 1988 as a Research Staff Member. ...
His interests include superconductor and semiconductor device physics, modeling and measurement, circuit design, and percolation in two-dimensional systems. Paul M. ...
ACKNOWLEDGMENT The authors would like to acknowledge the contributions of the Silicon Innovation Laboratory for fabricating the devices described in this paper. ...
doi:10.1109/5.752515
fatcat:siz3jry7hjctlkjesyr5s6vh2m
The scaling challenge
2003
Proceedings of the 2003 international symposium on Physical design - ISPD '03
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We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. ...
We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. ...
Placement and Routing The post-RTL design stage that sees the biggest impact due to the exploding repeater count is that of placement. ...
doi:10.1145/640000.640014
dblp:conf/ispd/SaxenaMCK03
fatcat:kc7ebjlnynaizcxsinn4q3k5dm
The scaling challenge
2003
Proceedings of the 2003 international symposium on Physical design - ISPD '03
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We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. ...
We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. ...
Placement and Routing The post-RTL design stage that sees the biggest impact due to the exploding repeater count is that of placement. ...
doi:10.1145/640012.640014
fatcat:nc52vj4sbncgjdsddnkrbwns2i
Repeater Scaling and Its Impact on CAD
2004
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Finally, we suggest a few approaches to tackle these challenges, by constructing a case for flexible, abstract fabrics that follow correct-by-construction design principles. ...
In particular, we study the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for physical synthesis and full-chip assembly, showing ...
will no longer be viable as a post-placement afterthought. ...
doi:10.1109/tcad.2004.825841
fatcat:c6ewrpj5kjeg3adybic6lha2qy
Ultralow-voltage, minimum-energy CMOS
2006
IBM Journal of Research and Development
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Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy use. ...
In this work, we review circuit behavior at low voltages, specifically in the subthreshold (V dd , V th ) regime, and suggest new strategies for energy-efficient design. ...
Alternatively, logic may be partitioned for placement in specific voltage islands with independent supplies that are compiler-controlled [26] . ...
doi:10.1147/rd.504.0469
fatcat:uoxjtjd4xjfind6lwghkmrutgm
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