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Post-compaction register assignment in a retargetable compiler

P. Sweany, S. Beaty
[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture  
We discuss graph-coloring register assignment in a retargetable compiler for Long-Instruction-Word architectures.  ...  Of specific concern is when, during the compilation process, should register assignment be performed. We conclude that, for best results, register assignment should follow compaction.  ...  implementation issues involved in post-compaction register assignment.  ... 
doi:10.1109/micro.1990.151432 fatcat:xhbmidhejrhmzoh3rvt6ezwidq

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
1999 Proceedings of the seventh international workshop on Hardware/software codesign - CODES '99  
If the compiler were to perform compaction after memory bank allocation and register assignment, then the quality of the compacted code could suffer (due to the stringent memory bank allocation and register  ...  The Elixir compiler performs compaction before variables have been allocated to memory banks and symbolic registers have been assigned to physical registers.  ...  Given a sequence of array accesses within a loop, the array index allocation optimization [1] utilizes the auto-increment capability of the address registers in order to efficiently walk through the elements  ... 
doi:10.1145/301177.301184 dblp:conf/codes/RajanFSM99 fatcat:zj25r2dfa5ft7am6lvyvx4i5la

Address calculation for retargetable compilation and exploration of instruction-set architectures

Clifford Liem, Pierre Paulin, Ahmed Jerraya
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
This paper introduces a new retargetable approach and prototype tool for the analysis of array references and traversals for efficient use of ACUs.  ...  Since access to data is often the most demanding task in DSP, this mapping can be the most crucial function of the compiler.  ...  Note that the assignment cost for index registers is a value dependent on the order of pointer assignment.  ... 
doi:10.1145/240518.240631 dblp:conf/dac/LiemPJ96 fatcat:pprqehbvarde7ld4zwpbmeaxwm

The very portable optimizer for digital signal processors

Sungjoon Jung, Yunheung Paek
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architectural variations of DSPs  ...  The compiler was originally implemented to target among GPPs, but thanks to its novel intermediate representation designed to support retargetability, it has been successfully retargeted at a commercial  ...  Covered ETs are passed to a scheduling phase, to an address assignment phase and finally to a compaction phase. The final result is a binary machine code listing, not an assembly code.  ... 
doi:10.1145/502225.502230 fatcat:zlqic2w6xzdgtaadmtayfbggjy

The very portable optimizer for digital signal processors

Sungjoon Jung, Yunheung Paek
2001 Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01  
Although retargetability has been a major design concern for many compilers, retargetability is a vitally important issue for Digital Signal Processors(DSPs) because the architectural variations of DSPs  ...  The compiler was originally implemented to target among GPPs, but thanks to its novel intermediate representation designed to support retargetability, it has been successfully retargeted at a commercial  ...  Covered ETs are passed to a scheduling phase, to an address assignment phase and finally to a compaction phase. The final result is a binary machine code listing, not an assembly code.  ... 
doi:10.1145/502217.502230 dblp:conf/cases/JungP01 fatcat:ggf3w6l6qrb67hyp2yzdjfd4q4

Predicting performance potential of modern DSPs

Naji Ghazal, Richard Newton, Jan Rabaey
2000 Proceedings of the 37th conference on Design automation - DAC '00  
In this paper we describe our approach to Retargetable Estimation and show how and why it can be effective in quickly predicting and guiding toward hand-optimized performance of moderns DSPs for a given  ...  We also contrast the advantages of this scheme with those of a full-featured optimizing compiler.  ...  To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.  ... 
doi:10.1145/337292.337431 dblp:conf/dac/GhazalNR00 fatcat:6fxcc774pjbgtl2xqizab3lce4

Embedded software in real-time signal processing systems: design technologies

G. Goossens, J. Van Praet, D. Lanneer, W. Geurts, A. Kifli, C. Liem, P.G. Paulin
1997 Proceedings of the IEEE  
A companion paper in this issue [1] presents a survey of application and architecture trends for embedded systems in these growth markets.  ...  The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries.  ...  Register Allocation In the register allocation phase, the compiler assigns intermediate computation values to storage locations in the processor.  ... 
doi:10.1109/5.558718 fatcat:jtn2aeo4ybcwfgc67rdsdqjhei

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays

Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei
2008 Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '08  
Different register file models are studied and evaluated on a state-of-the art coarse-grained reconfigurable array DSP, together with a new post-pass register allocator for rotating register files.  ...  For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering problems.  ...  We have also presented more compact models that can be used to perform cluster or bank assignment and value replication as part of the routing, but which require a post-pass register allocator to perform  ... 
doi:10.1145/1375657.1375678 dblp:conf/lctrts/SutterCAM08 fatcat:aamtgreesva5pkxp5x5s2vh54y

Retargeting Android applications to Java bytecode

Damien Octeau, Somesh Jha, Patrick McDaniel
2012 Proceedings of the ACM SIGSOFT 20th International Symposium on the Foundations of Software Engineering - FSE '12  
The resulting Dare tool uses a new intermediate representation to enable fast and accurate retargeting.  ...  We evaluate Dare on 1,100 of the top applications found in the free section of the Android market and successfully retarget 99.99% of the 262,110 associated classes.  ...  Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.  ... 
doi:10.1145/2393596.2393600 dblp:conf/sigsoft/OcteauJM12 fatcat:bzptnvpbvrezdipm5kyrqp7c4y

Architecture Description Languages for Retargetable Compilation [chapter]

Sharad Malik, Wei Qin
2007 The Compiler Design Handbook  
In contrast, semi-retargetable and retargetable compilers aim to reuse at least part of the compiler back-end by factoring out target dependent information into machine description systems.  ...  Since it is desirable to evaluate multiple candidates, a retargetable compiler (and simulator) is highly desirable.  ...  However, for users interested in retargetable compiler development only, describing a processor at the RT-level can be quite a tedious process.  ... 
doi:10.1201/9781420043839.ch16 fatcat:6uszortfbzadpiu47wqepfz3p4

Architecture Description Languages for Retargetable Compilation [chapter]

Wei Qin, Sharad Malik
2002 The Compiler Design Handbook  
In contrast, semi-retargetable and retargetable compilers aim to reuse at least part of the compiler back-end by factoring out target dependent information into machine description systems.  ...  Since it is desirable to evaluate multiple candidates, a retargetable compiler (and simulator) is highly desirable.  ...  However, for users interested in retargetable compiler development only, describing a processor at the RT-level can be quite a tedious process.  ... 
doi:10.1201/9781420040579.ch14 fatcat:sa3eihqbqjdv3bzdh3wsuuyzaa

Software synthesis and code generation for signal processing systems

S.S. Bhartacharyya, R. Leupers, P. Marwedel
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This paper reviews the state-of-the-art in programming language and compiler technology for DSP software implementation.  ...  optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations.  ...  file sizes, or interconnect structure. 2) Further Retargetable Compilers: A widespread example for a retargetable compiler is the GNU compiler "gcc" [88] .  ... 
doi:10.1109/82.868454 fatcat:4udasl3dqnekthi5ymwgttnuti

Ashli – Advanced Shading Language Interface [article]

Arcot J. Preetham, Avi Bleiweiss
2003 Eurographics State of the Art Reports  
The support for IEEE floating point computation and the exposure of shading functionality in a standardize API form have made graphics hardware a viable workflow solution to an artist involved in digital  ...  Ashli is developed in the form of a case study. It takes in high level shading languages and descriptions and at the end emits standard graphics hardware shading API (e.g.  ...  Imaging Ashli supports image-processing operations on a post-rendered image in the context of an imager shader.  ... 
doi:10.2312/egp.20031027 fatcat:k7zdcq45jzbxfgvbfk4tto4pwi

Free Rider

Stanislav Manilov, Björn Franke, Anthony Magrath, Cedric Andrieu
2015 Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM - LCTES'15  
In this paper we develop a novel methodology for retargeting such non-portable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform.  ...  These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialised compiler support.  ...  Modelling of instruction semantics in ADL processor descriptions for C compiler retargeting has been presented in [4] .  ... 
doi:10.1145/2670529.2754962 dblp:conf/lctrts/ManilovFMA15 fatcat:jeo5pkmd7jgurmz5wipekiyive

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda
2010 Journal of Supercomputing  
This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computationbased processor.  ...  Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore.  ...  We tried to develop a queue compiler based on a retargetable compiler for register machines [7] .  ... 
doi:10.1007/s11227-010-0409-z fatcat:bkijujepezcfxhek2visg4fpw4
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