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Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

Denis Becker, Matthieu Moy, Jérôme Cornet
2016 Electronics  
The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations.  ...  There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/electronics5020022 fatcat:hof7wuibzna5vkgishdfisqsmy

On the validation of embedded systems through functional ATPG

Giuseppe Di Guglielmo
2008 2008 Ph.D. Research in Microelectronics and Electronics  
The methods of the SystemC-QEmu wrapper are sensitive to these ports: whenever a data is received on a port, the corresponding method is called in order to update the wrapper registers and eventually trigger  ...  In particular, it discusses how to benefit from the use of gate-level parallel simulation techniques for simulating functional-level faults, along with the issues implied by porting parallel simulation  ... 
doi:10.1109/rme.2008.4595747 fatcat:y7p3ujfoqveb5grdq3bbowscbu

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems

Luca Ramini, Herve Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortin-Obon, Anja Boos, Sandro Bartolini
2014 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)  
The consistency of the outlined approach is verified, in the first instance, by performing a SystemC analysis of a four input and four output ports switch, and making a comparison with the results of 2D-FDTD  ...  Down, Simulated (solid line) and modeled (dashed line) transmission curves for the paths linking the I-WEST port with the O-NORTH port and I-WEST port with the O-SOUTH port of the 4x4 Optical Switch. .  ... 
doi:10.1109/nocs.2014.7008778 dblp:conf/nocs/RaminiFGGOBB14 fatcat:rfhirddgcrflld2hjkb24ajzti

Methods for evaluating and covering the design space during early design development

Matthias Gries
2004 Integration  
It is focused on System-on-a-Chip designs, particularly those used for network processors.  ...  This paper gives an overview of methods used for Design Space Exploration (DSE) at the system-and micro-architecture levels.  ...  Kulkarni, and the Mescal team for valuable discussions and comments.  ... 
doi:10.1016/j.vlsi.2004.06.001 fatcat:3m3nshpmgvcvriwsh3cpd2iga4

Methods for evaluating and covering the design space during early design development

M GRIES
2004 Integration  
It is focused on System-on-a-Chip designs, particularly those used for network processors.  ...  This paper gives an overview of methods used for Design Space Exploration (DSE) at the system-and micro-architecture levels.  ...  Kulkarni, and the Mescal team for valuable discussions and comments.  ... 
doi:10.1016/s0167-9260(04)00032-x fatcat:j7mgqssclnehrbszo7ktv64edq

Techniques for LI-BDN synthesis for hybrid microarchitectural simulation

Tyler S. Harris, Zhuo Ruan, David A. Penry
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
Techniques for LI-BDN Synthesis for Hybrid Microarchitectural Simulation Tyler S.  ...  Hybrid simulators which offload some of the simulation work onto FPGAs can increase the speed; however, such simulators must be automatically synthesized or the time to design them becomes prohibitive.  ...  SystemC Process Synthesis Hybrid simulator synthesizers transform SystemC processes into FPGA hardware. We will call the generated hardware FPGA-implemented Processes (FIPs).  ... 
doi:10.1109/iccd.2011.6081405 dblp:conf/iccd/HarrisRP11 fatcat:v5fhgauqjjfy3inpgh77pe4ahy

System Based Interference Analysis in Capella

Amin Oueslati, Philippe Cuenot, Julien Deantoni, Christophe Moreno
2019 Journal of Object Technology  
instance, on parallel coordinates chart.  ...  The simulation is done by translation of the model element to (predefined) SystemC blocks.  ... 
doi:10.5381/jot.2019.18.2.a14 fatcat:b4gu6hydsjfzppjublhvzsyifm

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

F. Gilabert, D. Ludovici, S. Medardoni, D. Bertozzi, L. Benini, G.N. Gaydadjiev
2009 2009 International Conference on Complex, Intelligent and Software Intensive Systems  
From a technology viewpoint, interconnect reverse scaling causes critical paths to go across global links.  ...  for these systems, borrowed from the domain of off-chip interconnection networks.  ...  Our previous work in [24] presents silicon-aware topology analysis for a network with 16 nodes.  ... 
doi:10.1109/cisis.2009.30 dblp:conf/cisis/VillamonLMBBG09 fatcat:ebynnnt4pzg7voy7o32dmfbbee

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, Zhiru Zhang
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
for FPGA designs.  ...  Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially  ...  The method in [19] presents a theorem to capture all possible reference conflicts under cyclic partitioning in a data structure called a conflict graph.  ... 
doi:10.1109/tcad.2011.2110592 fatcat:rr75vomr6zf5vhgs3swjblslza

Efficient multi-level fault simulation of HW/SW systems for structural faults

Rafal Baranowski, Stefano Di Carlo, Nadereh Hatami, Michael E. Imhof, Michael A. Kochte, Paolo Prinetto, Hans-Joachim Wunderlich, Christian G. Zoellin
2011 Science China Information Sciences  
The analysis of this interaction at early design stages gives important feedback for reliable [6, 7] and secure systems [8] .  ...  Efficient multi-level fault simulation of HW/SW systems for structural faults.  ...  Acknowledgements The authors thank Giorgio Di Natale for providing the source code of the self-testable AES core developed at The Montpellier Laboratory of Informatics, Robotics, and Microelectronics (  ... 
doi:10.1007/s11432-011-4366-9 fatcat:37ddbwbf5vbplj4hbz24nz3gea

Development and validation of Nessie: a multi-criteria performance estimation tool for SoC

Alienor Richard, Cedric Hernalsteens, Frederic Robert
2009 2009 Ph.D. Research in Microelectronics and Electronics  
The support for models and simulations is SystemC.  ...  This particular extension is called MARTE 6 for "Modeling and Analysis of Real-time and Embedded" systems.  ...  have still produce results for the first model to make comparison and analysis based on the 11 first architecture variants. 2.  ... 
doi:10.1109/rme.2009.5201349 fatcat:lk2x6luvzzfopl24okg723lfhu

Formal verification in a component-based reuse methodology

Daniel Karlsson, Petru Eles, Zebo Peng
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
As a common basis, these techniques have been developed using a Petri net based modelling approach, called PRES+.  ...  The second technique involves a simulation based approach into which formal methods are injected to boost verification efficiency.  ...  These procedures are called once for each port in the interface of the stub. traceBack is called for out-ports and traceForward in the case of in-ports. visited is a mapping from places and transitions  ... 
doi:10.1145/581199.581235 fatcat:h6jzwdpw2zbbhmq34qijsn3ani

Formal ESL Synthesis for Control-Intensive Applications

Michael F. Dossis
2012 Advances in Software Engineering  
The authors in [43] assume that the computational complexity of flow-sensitive and context-sensitive analysis is not high because of the small size and simplicity of the programs and function calls which  ...  These optimizations utilize techniques such as clique partitioning, path analysis, and symbolic simulation.  ... 
doi:10.1155/2012/156907 fatcat:f55w3dv6crflzfqinksfrcahnu

A survey of research and practices of Network-on-chip

Tobias Bjerregaard, Shankar Mahadevan
2006 ACM Computing Surveys  
We also evaluate performance analysis techniques.  ...  In DSM technologies, the wire models are unreliable, due to issues like fabrication uncertainties, crosstalk, noise sensitivity etc. These issues are especially applicable to long wires.  ...  ACKNOWLEDGEMENTS We would like to thank professors Jens Sparsø and Jan Madsen of the Department for Informatics and Mathematical Modelling (IMM) at the Technical University of Denmark (DTU) for their tireless  ... 
doi:10.1145/1132952.1132953 fatcat:kpaihucc7rbqfg2ujtg7xubbqq

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Jose Ricardo Gomez-Rodriguez, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Ivan Rodriguez-Abdala, Jose Luis Vazquez-Avila, Ramon Parra-Michel
2021 Micromachines  
Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements.  ...  Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/mi12020183 pmid:33673049 fatcat:mwlekxzfpfhwhbegwwyio4kaaq
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