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Polymorphic On-Chip Networks

Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd Austin
2008 SIGARCH Computer Architecture News  
We propose polymorphic on-chip networks to enable perapplication network customization.  ...  Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network  ...  We explore the polymorphic network design space by instantiating the networks composing the initial network-on-chip design space in each candidate polymorphic design.  ... 
doi:10.1145/1394608.1382131 fatcat:wrhq7u66s5hwbb4celwzeizany

Polymorphic On-Chip Networks

Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd Austin
2008 2008 International Symposium on Computer Architecture  
We propose polymorphic on-chip networks to enable perapplication network customization.  ...  Finally, we expand the network on chip design space to include a polymorphic network design, showing that a single polymorphic network is capable of implementing all of the pareto optimal fixed-network  ...  We explore the polymorphic network design space by instantiating the networks composing the initial network-on-chip design space in each candidate polymorphic design.  ... 
doi:10.1109/isca.2008.25 dblp:conf/isca/KimDOA08 fatcat:xucwu54uxvdmtk2u4wu2qvhtje

Cubic Ring Networks: A Polymorphic Topology for Network-on-Chip

Bilal Zafar, Jeff Draper, Timothy M. Pinkston
2010 2010 39th International Conference on Parallel Processing  
As chip multiprocessors transition from multi-core to many-core, on-chip network power is increasingly becoming a key barrier to scalability.  ...  Studies have shown that on-chip networks can consume up to 36% of the total chip power, while analysis of network traffic reveals that for extended periods of execution time, network load is well below  ...  This polymorphic topology provides a simple yet flexible infra-structure for on-demand bandwidth provisioning in on-chip networks.  ... 
doi:10.1109/icpp.2010.52 dblp:conf/icpp/ZafarDP10 fatcat:evwi7sfelzarfg6limxkcfibci

Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems

Maziar Goudarzi, Naser MohammadZadeh, Shaahin Hessabi
2007 Journal of computer and system sciences (Print)  
The Network-on-Chip (NoC) paradigm brings networks inside chips.  ...  Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT.  ...  Polymorphism in a network-on-chip Our NoC architecture and its components are given in Fig. 1 .  ... 
doi:10.1016/j.jcss.2007.02.009 fatcat:tjclxdf6jjglljyccse7owyvcm

SAPA: Self-Aware Polymorphic Architecture [article]

Michel A. Kinsy, Mihailo Isakov, Alan Ehret, Donato Kava
2018 arXiv   pre-print
It has heterogeneous reconfigurable cores with fast hardware-level migration capability, self-organizing memory structures and hierarchies, an adaptive application-aware network-on-chip, and a built-in  ...  In this work, we introduce a Self-Aware Polymorphic Architecture (SAPA) design approach to support emerging context-aware applications and mitigate the programming challenges caused by the ever-increasing  ...  The on-chip network of active processing elements expands and contracts dynamically during runtime depending on the program execution needs and performancepower targets.  ... 
arXiv:1802.05100v1 fatcat:txc5huhv2faqjmsawq55ujpfp4

Reconfigurable Digital Circuits Based on Chip Expander with Integrated Temperature Regulation

Vaclav Simek, Richard Ruzicka, Adam Crha, Michal Reznicek
2015 Journal of Computer and Communications  
Real application of the developed chip expander platform is demonstrated in context of digital reconfigurable circuits based on polymorphic electronics.  ...  In this case the chip expander with attached polymorphic chip REPOMO is thermally stabilized at an ambient temperature level up to approximately 135˚C and its sensitivity to this phenomenon is demonstrated  ...  Figure 3 . 3 Behaviour of the polymorphic FIR filter section in REPOMO chip on the developed chip expander platform.  ... 
doi:10.4236/jcc.2015.311027 fatcat:5jgsdobrgfg5pcqbvwtc36mqca

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism.  ...  This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism.  ...  This paper proposes and describes the polymorphous TRIPS architecture, which uses the partitioning approach, combining coarse-grained polymorphous Grid Processor cores with an adaptive, polymorphous on-chip  ... 
doi:10.1145/859618.859667 fatcat:w2yv6e2ixjhmrjc2sigtq7ms2y

Exploiting ILP, TLP, and DLP with the polymorphous trips architecture

K. Sankaralingam, R. Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, D. Burger, S.W. Keckler, C. Moore
2003 IEEE Micro  
TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism.  ...  This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism.  ...  This paper proposes and describes the polymorphous TRIPS architecture, which uses the partitioning approach, combining coarse-grained polymorphous Grid Processor cores with an adaptive, polymorphous on-chip  ... 
doi:10.1109/mm.2003.1261386 fatcat:fdvstyrrfnbsji6ta6hvuv6mb4

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism.  ...  This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism.  ...  This paper proposes and describes the polymorphous TRIPS architecture, which uses the partitioning approach, combining coarse-grained polymorphous Grid Processor cores with an adaptive, polymorphous on-chip  ... 
doi:10.1145/859666.859667 fatcat:cqimown4gbahxpre5vw6ee2pm4

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
2003 SIGARCH Computer Architecture News  
TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism.  ...  This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism.  ...  This paper proposes and describes the polymorphous TRIPS architecture, which uses the partitioning approach, combining coarse-grained polymorphous Grid Processor cores with an adaptive, polymorphous on-chip  ... 
doi:10.1145/871656.859667 fatcat:y2tkcq2z6ze7ljgxdfxjaswp2m

REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware

Lukas Sekanina, Richard Ruzicka, Zdenek Vasicek, Roman Prokop, Lukas Fujcik
2009 2009 IEEE Workshop on Evolvable and Adaptive Hardware  
In this paper, a new reconfigurable polymorphic chip (REPOMO32) is introduced.  ...  This chip has been developed in order to investigate the electrical properties of polymorphic circuits and demonstrate the applications of polymorphic electronics.  ...  On the basis of these investigations the final architecture of REPOMO32 was defined and the chip was fabricated in 2008. Figure 1 shows the structure of the chip.  ... 
doi:10.1109/weah.2009.4925666 dblp:conf/weah/SekaninaRVPF09 fatcat:3fwaeohlw5ex7kdxexsefgzu2y

Supporting Sensing Enterprise Operations with Polymorphic ServiceInfrastructures

Anthony Karageorgos, Nikolay Mehandjiev, Elli Rapti
2014 IFAC Proceedings Volumes  
In this paper we propose a serviceoriented infrastructure for supporting sensing enterprise operations which is based on polymorphic services.  ...  The created networks are also connected to the internet which enables the nodes to search for candidate services on the cloud.  ...  Polymorphic behaviour in services can be exhibited either on the composed services or before and during service composition.  ... 
doi:10.3182/20140824-6-za-1003.02280 fatcat:s6o4wpsuqbam7mfivx55kxfjb4

Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit

Lukas Sekanina, Richard Ruzicka, Zdenek Vasicek, Vaclav Simek, Petr Hanacek
2013 Information Technology and Control  
We applied a partial reconfiguration in order to generate 48-bit IDs on the reconfigurable polymorphic REPOMO32 chip that we have developed in our previous research.  ...  In this paper, we investigate the use of polymorphic gates as a new mechanism for implementing a unique chip ID in systems already containing some polymorphic gates.  ...  Theoretical research in this area has lead to a new completeness theory for polymorphic Boolean networks [7] .  ... 
doi:10.5755/j01.itc.42.1.925 fatcat:5zpztrxmsnepncv5cn2fkx6nye

PBuf: An On-Chip Packet Transfer Engine for MONARCH

Rashed Zafar Bhatti, Craig Steele, Jeff Draper
2006 The ... Midwest Symposium on Circuits and Systems conference proceedings  
This paper describes the architecture and implementation of an on-chip packet interface/router called the Packet Buffer (PBuf) employed in the MOrphable Networked microARCHitecture (MONARCH).  ...  The PBuf provides protected translation in the midst of superior and inferior address spaces while also serving as an on-chip packet switching router.  ...  MONARCH implements two types of on-chip point-to-point packet switched ring networks, namely (1) Node Ring Network and (2) PIRX Ring Networks.  ... 
doi:10.1109/mwscas.2006.381784 fatcat:raa3epwovfeuxg3bg6mjibqqfq

Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture

David Hentrich, Erdal Oruklu, Jafar Saniie
2011 Circuits and Systems  
Polymorphic computing is widely seen as next evolutionary step in designing advanced computing architectures.  ...  This paper presents a brief history of reconfigurable and polymorphic computing, and highlights the recent trends and challenges.  ...  A company called Tilera now offers Raw architecture chips commercially. Thus far, the Tilera chips have seen success in network switches.  ... 
doi:10.4236/cs.2011.24049 fatcat:pucxxlzzwzcadht2eueb37otxm
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