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Point Neurons with Conductance-Based Synapses in the Neural Engineering Framework [article]

Andreas Stöckel, Aaron R. Voelker, Chris Eliasmith
2017 arXiv   pre-print
The mathematical model underlying the Neural Engineering Framework (NEF) expresses neuronal input as a linear combination of synaptic currents.  ...  In this technical report we first summarize the relevant portions of the NEF and conductance-based synapse models.  ...  Introduction As a central assumption, the Neural Engineering Framework (NEF, [1] ) relies on linear interaction of pre-synaptic activity in the form of synaptic currents injected into the neuron membrane  ... 
arXiv:1710.07659v1 fatcat:jazmrkz6afa5zijxtx65w3y7qm

NEVESIM: event-driven neural simulation framework with a Python interface

Dejan Pecevski, David Kappel, Zeno Jonke
2014 Frontiers in Neuroinformatics  
It supports simulation of heterogeneous networks with different types of neurons and synapses, and can be easily extended by the user with new neuron and synapse types.  ...  Altogether, the intended purpose of the NEVESIM framework is to provide a basis for further extensions that support simulation of various neural network models incorporating different neuron and synapse  ...  The NEVESIM simulator was developed by Dejan Pecevski with contributions from David Kappel.  ... 
doi:10.3389/fninf.2014.00070 pmid:25177291 pmcid:PMC4132371 fatcat:l27ob3vuqracfj4tdsfeomxqvi

Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system

Daniel Briiderle, Johannes Bill, Bernhard Kaplan, Jens Kremkow, Karlheinz Meier, Eric Muller, Johannes Schemmel
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
We utilize a mixed-signal VLSI model that implements a massively accelerated network of spiking neurons, and we describe a novel methodological framework that allows to exploit both the speed and the programmability  ...  The presented hardware experiments include highconductance states in hardware neurons and the application of synaptic depression and facilitation for self-adjusting network architectures. 978-1-4244-5309  ...  with existing conductance-based modeling approaches [15] .  ... 
doi:10.1109/iscas.2010.5537005 dblp:conf/iscas/BruderleBKKMMS10a fatcat:pu2y2queyzf2ddnrfowbaykyqy

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets

Abhronil Sengupta, Yong Shim, Kaushik Roy
2016 IEEE Transactions on Biomedical Circuits and Systems  
The device offers a direct mapping to synapse and neuron functionalities in the brain while inter-layer network communication is accomplished via CMOS transistors.  ...  Non-Boolean computing based on emerging post-CMOS technologies can potentially pave the way for low-power neural computing platforms.  ...  Spintronic synapses are present at each cross-point of the array and the domain wall position in the device encodes the value of the corresponding synaptic weight or conductance.  ... 
doi:10.1109/tbcas.2016.2525823 pmid:27214912 fatcat:k4us2wbg3feo7pflsjxxivnb54

Complex Learning in Bio-plausible Memristive Networks

Lei Deng, Guoqi Li, Ning Deng, Dong Wang, Ziyang Zhang, Wei He, Huanglong Li, Jing Pei, Luping Shi
2015 Scientific Reports  
The emerging memristor-based neuromorphic engineering promises an efficient computing paradigm.  ...  The requirements of this framework are three-fold: (1) suitable device to model the synaptic plasticity; (2) bio-plausible recurrent neural network with ongoing internal dynamics; (3) efficient learning  ...  Acknowledgements Financial supports from the National Natural Science Foundation of China (No. 61475080) and the Study of Brain-Inspired Computing System of Tsinghua University (No. 20141080934) are acknowledged  ... 
doi:10.1038/srep10684 pmid:26090862 pmcid:PMC4473596 fatcat:mhj4iza3uzeillb7ffku6hogse

Systematic configuration and automatic tuning of neuromorphic systems

Sadique Sheik, Fabio Stefanini, Emre Neftci, Elisabetta Chicca, Giacomo Indiveri
2011 2011 IEEE International Symposium of Circuits and Systems (ISCAS)  
, to the development of object oriented classes and methods in software; from electrical engineering and physics for analog/digital circuit design to neuroscience and computer science for neural computation  ...  Within this context, we present a framework we developed to simplify the configuration of multi-chip neuromorphic VLSI systems, and automate the mapping of neural network model parameters to neuromorphic  ...  The authors would like to thank the NCS group ( for contributing to the development of the AER and multi-chip experimental setups.  ... 
doi:10.1109/iscas.2011.5937705 dblp:conf/iscas/SheikSNCI11 fatcat:umo2lfryzzdsxkbosjvvrcz4ra

Toward Fast Neural Computing using All-Photonic Phase Change Spiking Neurons

Indranil Chakraborty, Gobinda Saha, Abhronil Sengupta, Kaushik Roy
2018 Scientific Reports  
We also show that such a neuron can be potentially integrated with on-chip synapses into an all-Photonic Spiking Neural network inferencing framework which promises to be ultrafast and can potentially  ...  functional units of the brain, namely, neurons and synapses.  ...  Acknowledgements The work was supported in part by, ONR-MURI program, the National Science Foundation, Intel Corporation and by the DoD Vannevar Bush Fellowship.  ... 
doi:10.1038/s41598-018-31365-x pmid:30154507 fatcat:4xsp2noljjggtlcomnprodfgdy

Temporal constrained objects for modelling neuronal dynamics

Manjusha Nair, Jinesh Manchan Kannimoola, Bharat Jayaraman, Bipin Nair, Shyam Diwakar
2018 PeerJ Computer Science  
The structural aspects of a neuronal system are represented using objects, as in object-oriented languages, while the dynamic behaviour of neurons and synapses are modelled using declarative temporal constraints  ...  Results We identified the feasibility and practicality in automatically mapping different kinds of neuron and synapse models to the constraints of temporal constrained objects.  ...  The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.  ... 
doi:10.7717/peerj-cs.159 pmid:33816812 pmcid:PMC7924700 fatcat:562afavawrbbdmcoaccoeq5m2m

Data and Power Efficient Intelligence with Neuromorphic Learning Machines

Emre O. Neftci
2018 iScience  
The success of deep networks and recent industry involvement in brain-inspired computing is igniting a widespread interest in neuromorphic hardware that emulates the biological processes of the brain on  ...  We suggest that a neuromorphic learning framework, tuned specifically for the spatial and temporal constraints of the neuromorphic substrate, will help guiding hardware algorithm co-design and deploying  ...  ACKNOWLEDGMENTS This work was partly supported by the Intel Corporation, the National Science Foundation under grant 1652159, and by the Korean Institute of Science and Technology.  ... 
doi:10.1016/j.isci.2018.06.010 pmid:30240646 pmcid:PMC6123858 fatcat:zo4dvtgo75c7pn6n7tal24fkly

TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design

Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2017 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)  
In this work, we propose TraNNsformer - an integrated training framework that transforms DNNs to enable their efficient realization on MCA-based systems.  ...  Eventually they produce DNNs with highly inefficient hardware realizations (in terms of area and energy).  ...  MLPs are a class of neural networks with fully connected topology i.e. each neuron in a layer receives inputs from all the neurons in the previous layer.  ... 
doi:10.1109/iccad.2017.8203823 dblp:conf/iccad/AnkitS017 fatcat:gd4i2wzberb5bgbbv4czuvdv24

Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator

O. Bichler, D. Roclin, C. Gamrat, D. Querlioz
2013 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)  
hardware description languages and high-level neural networks simulators used primarily in neurosciences.  ...  This simulator was used to establish several results on Spike-Timing-Dependent Plasticity (STDP) modeling and implementation with Resistive RAM (RRAM), Conductive Bridge RAM (CBRAM) and Phase-Change Memory  ...  The insets show the weights map of an output neuron after the learning of the car sequence, for four sets of parameter obtained at different point in the genetic evolution. IV. EVENT-BASED VS.  ... 
doi:10.1109/nanoarch.2013.6623029 dblp:conf/nanoarch/BichlerRGQ13 fatcat:ldaktbfxnjaexjt4zvrlr7fisq

FPGA Based Platform for Spiking Neural Network

Devanshi Raval
2017 International Journal for Research in Applied Science and Engineering Technology  
Neuromorphic engineers are studying the nervous system and trying to emulate its function and organization in their computational and robotics systems.  ...  They are hoping to match the human brain in vision, hearing, pattern recognition and learning tasks.  ...  The proposed FPGA design framework is based on a reconfigurable neural layer, which is implemented using a time-multiplexing approach to achieve up to 200,000 virtual neurons with one physical neuron using  ... 
doi:10.22214/ijraset.2017.3076 fatcat:ffknumobzrbilplytwhm7lgeha

Neuromorphic Electronic Systems for Reservoir Computing [article]

Fatemeh Hadaeghi
2020 arXiv   pre-print
Moreover, to deal with challenges of computation on such unconventional substrates, several lines of potential solutions are presented based on advances in other computational approaches in machine learning  ...  Here, a review of these experimental studies is provided to illustrate the progress in this area and to address the technical challenges which arise from this specific hardware implementation.  ...  This similarity has paved the way towards the fabrication of compact analog circuits that implement electronic models of voltage-sensitive conductance-based neurons and conductance-based synapses as well  ... 
arXiv:1908.09572v2 fatcat:cimkbnvyrjc3lhixlyufgmqy3i

Spin-Based Neuron Model With Domain-Wall Magnets as Synapse

M. Sharad, C. Augustine, G. Panagopoulos, K. Roy
2012 IEEE transactions on nanotechnology  
The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power.  ...  CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices.  ...  Acknowledgement This research was funded in part by Nano Research Initiative and by the INDEX center.  ... 
doi:10.1109/tnano.2012.2202125 fatcat:exgx4wwz7rfibbo5k2vhyj57ju

Passive nonlinear dendritic interactions as a general computational resource in functional spiking neural networks [article]

Andreas Stöckel, Chris Eliasmith
2020 arXiv   pre-print
In this paper, we present a series of extensions to the Neural Engineering Framework that facilitate the construction of networks incorporating Dale's principle and nonlinear conductance-based synapses  ...  We show that it is possible to incorporate neuron models with input-dependent nonlinearities into the Neural Engineering Framework without compromising high-level function and that nonlinear post-synaptic  ...  Voelker for his comments on earlier drafts of this paper, as well as his advice and constructive criticism regarding the conducted experiments.  ... 
arXiv:1904.11713v2 fatcat:vlfpwsckpbawfpwpmye6lxibym
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