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FPGA based Parallelized Architecture of Efficient Graph based Image Segmentation Algorithm [article]

Roopal Nahar, Akanksha Baranwal, K.Madhava Krishna
2017 arXiv   pre-print
parallelism as the way forward to achieve higher acceleration.  ...  They exceed the computing speed of software based implementations by breaking the paradigm of sequential execution and accomplishing more per clock cycle operations by enabling hardware level parallelization  ...  CONCLUSION AND FUTURE SCOPE Implementing a software algorithm on an FPGA enables us to exploit the hardware flexibility, parallelization, logical, electrical and physical advantages of it.  ... 
arXiv:1710.02260v1 fatcat:pprmflivdndu7hbyj4kq25hi54

Database Analytics: A Reconfigurable-Computing Approach

Bharat Sukhwani, Hong Min, Mathew Thoennes, Parijat Dube, Bernard Brezzo, Sameh Asaad, Donna Eng Dillenberger
2014 IEEE Micro  
Database analytics accelerator on FPGAs Our FPGA-accelerated database analytics system consists of an off-the-shelf host server with a PCI Express (PCIe)-attached FPGA accelerator card, and it runs a commercial  ...  His research interests include domain-optimized architectures and systems, reconfigurable computing, and FPGA-based application acceleration.  ... 
doi:10.1109/mm.2013.107 fatcat:lmc3lqdkijawpe75okpv6rwc4u

High Bandwidth Memory on FPGAs: A Data Analytics Perspective [article]

Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso
2020 arXiv   pre-print
HBM promises overcoming the bandwidth bottleneck, faced often by FPGA-based accelerators due to their throughput oriented design.  ...  In certain cases, FPGA+HBM based solutions are able to surpass the highest performance provided by either a 2-socket POWER9 system or a 14-core XeonE5 by up to 1.8x (selection), 12.9x (join), and 3.2x  ...  Inherent parallelism and capability of creating specialized processing pipelines make FPGAs a good target in cases such as sorting [46] , joins [10] , hashing [47] , regular expression matching [15  ... 
arXiv:2004.01635v1 fatcat:wrme53ej3bgarbeeadw7vvgvpe

In-memory database acceleration on FPGAs: a survey

Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee
2019 The VLDB journal  
While FPGAs have seen prior use in database systems, in recent years interest in using FPGA to accelerate databases has declined in both industry and academia for the following three reasons.  ...  Ease of programming is improving through support of shared coherent virtual memory between the host and the accelerator, support for higher-level languages, and domain-specific tools to generate FPGA designs  ...  The work in [130] studies the FPGA-based hash join and the FPGA-based sort-merge join, and claims that the sort-merge join outperforms the hash join when the data sets become larger.  ... 
doi:10.1007/s00778-019-00581-w fatcat:32edtb7frfh3xhpziks75lys3y

Multi-query Stream Processing on FPGAs

Mohammad Sadoghi, Rija Javed, Naif Tarafdar, Harsh Singh, Rohan Palaniappan, Hans-Arno Jacobsen
2012 2012 IEEE 28th International Conference on Data Engineering  
An FPGA is a cost-effective hardware acceleration solution that has the potential to excel at analyticsbased computations due to its inherent parallelism.  ...  Finally, in two parallel pipelines both active JCs are ran in parallel to carry out the join computation (Phase 1 of the join semantics) and for each active JC i , RB is invoked to overwrite the oldest  ... 
doi:10.1109/icde.2012.39 dblp:conf/icde/SadoghiJTSPJ12 fatcat:3ztsskxvdre2dmgrmybvjvbwpy

An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography

Xinyu Li, Omar Hammami
2009 International Journal of Reconfigurable Computing  
Fork-Join model-based software parallelization is explored to find out the best parallelization configuration.  ...  Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the  ...  Mesh-based architectures are suitable for data parallel and pipelined applications.  ... 
doi:10.1155/2009/631490 fatcat:kcrbtxmc7jgd3jptwwrxqcuqf4

MASCARA-FPGA cooperation model: Query Trimming through accelerators

Van Long Nguyen Huu, Laurent d'Orazio, Emmanuel Casseau, Julien Lallet
2021 33rd International Conference on Scientific and Statistical Database Management  
Therefore, in this paper, we propose a MASCARA-FPGA cooperation model and related major accelerators. We also explain the pipeline model in which multiple accelerators can run in parallel.  ...  Although MASCARA pointed out the expensive modules, we have not yet discussed an architecture in which they leverage the accelerators of Field Programmable Gate Array (FPGA).  ...  Pipeline model for multiple accelerators Because these MASCARA accelerators can be executed in parallel, we gain two main benefits: 1) We can apply a pipeline model to process the pair of (𝑄, 𝑆 𝑖 )  ... 
doi:10.1145/3468791.3468795 fatcat:vl5coxzkava7fi6lj7n7cnnpla

Accelerating Database Systems Using FPGAs: A Survey

Philippos Papaphilippou, Wayne Luk
2018 2018 28th International Conference on Field Programmable Logic and Applications (FPL)  
Database systems are key to a variety of applications, and FPGA-based accelerators have shown promise in supporting high-performance database systems.  ...  The review includes studies of database acceleration frameworks and accelerator implementations for various database operators.  ...  The support of the United Kingdom EPSRC (grant number EP/I012036/1, EP/L00058X/1, EP/L016796/1, EP/N031768/1 and EP/K034448/1), European Union Horizon 2020 Research and Innovation Programme (grant number  ... 
doi:10.1109/fpl.2018.00030 dblp:conf/fpl/PapaphilippouL18 fatcat:gcnfescocngjbkdysdzj3rhpvy

Is FPGA Useful for Hash Joins?

Xinyu Chen, Yao Chen, Ronak Bajaj, Jiong He, Bingsheng He, Weng-Fai Wong, Deming Chen
2020 Conference on Innovative Data Systems Research  
The hash join is one of the most costly operators in database systems and accelerating the hash join as a whole task on discrete FPGA platforms has been explored for a long time.  ...  However, the opportunities it brings to hash joins are still under-explored.  ...  This work is also partly supported by the National Research Foundation, Prime Minister's Office, Singapore under its Campus for Research Excellence and Technological Enterprise (CREATE) programme, and  ... 
dblp:conf/cidr/ChenCBHHWC20 fatcat:e2c7v2aclnd3llwfvmbmjz7mvy

FPGA-based Data Partitioning

Kaan Kara, Jana Giceva, Gustavo Alonso
2017 Proceedings of the 2017 ACM International Conference on Management of Data - SIGMOD '17  
Data partitioning is expensive, in some cases up to 90% of the cost of, e.g., a parallel hash join. In this paper we explore the use of an FPGA to accelerate data partitioning.  ...  Our experiments demonstrate that FPGA based partitioning is significantly faster and more robust than CPU based partitioning.  ...  Although absolute throughput numbers are not reported, it is stated that near memory join processing outperforms CPU-based ones for both hash and sort-based joins, through a highly parallelized design  ... 
doi:10.1145/3035918.3035946 dblp:conf/sigmod/KaraGA17 fatcat:qnrdla3b4vbmhazor7ivqftlxy

The FQP Vision

Mohammadreza Najafi, Mohammad Sadoghi, Hans-Arno Jacobsen
2015 SIGMOD record  
FQP is prototyped on field-programmable gate arrays (FPGAs). To this end, FQP supports select, project and window-join queries over data streams.  ...  The Flexible Query Processor (FQP) constitutes a family of hardware-based data stream processors that support dynamic changes to queries and streams, as well as static changes to the processor-internal  ...  It enables online changes to queries based on a number of parameters, including variable tuple size, projection attributes, selection conditions, join conditions, and join-window size.  ... 
doi:10.1145/2814710.2814712 fatcat:xcllfuofkzfgfa3bxxaz7lvjym

Acceleration of the Pair-HMM forward algorithm on FPGA with cloud integration for GATK

Rick Wertenbroek, Yann Thoma
2019 2019 IEEE International Conference on Bioinformatics and Biomedicine (BIBM)  
To speed-up computations we propose an FPGA based hardware accelerator for the Amazon AWS F1 Cloud platform.  ...  The accelerator is open source and has been tested within the popular Genomic Analysis Toolkit (GATK) pipeline.  ...  ACKNOWLEDGMENTS The authors would like to thank HEIG-VD for the funding of the Power Efficient Hardware Acceleration of Genomic Algorithms (PEHAGA) program which made this project possible, as well as  ... 
doi:10.1109/bibm47256.2019.8983189 dblp:conf/bibm/WertenbroekT19 fatcat:gqozey6l4rahxnh3vjifz7zdvu

The Glass Half Full: Using Programmable Hardware Accelerators in Analytics

Zsolt István
2019 IEEE Data Engineering Bulletin  
In the light of a shifting hardware landscape and emerging analytics workloads, it is time to revisit our stance on hardware acceleration.  ...  of specialization are seen to be outweighed by the limitations of the proposed solutions and the additional complexity of including specialized hardware, such as field programmable gate arrays (FPGAs)  ...  , David Sidler, Louis Woods and Jana Giceva.  ... 
dblp:journals/debu/Istvan19 fatcat:z7a3z66tzzg5xd4nizbz47guli

Compiling text analytics queries to FPGAs

Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
We evaluate the performance, power consumption and hardware utilization of our approach for a set of different queries compiled to a Stratix IV FPGA.  ...  We present a framework consisting of a compiler and an operator library capable of generating a Verilog processing pipeline from a text analytics query specified in the annotation query language AQL.  ...  We present an FPGA based accelerator architecture for the SystemT text analytics engine.  ... 
doi:10.1109/fpl.2014.6927500 dblp:conf/fpl/PoligAGC14 fatcat:scmijbpytvcynaiuhqf7lxsqky

Scotch: Generating FPGA-Accelerators for Sketching at Line Rate

Martin Kiefer, Ilias Poulakis, Sebastian Breß, Volker Markl
2020 Proceedings of the VLDB Endowment  
Our evaluation shows that FPGA accelerators generated by Scotch outperform CPU-and GPU-based sketching by up to two orders of magnitude in terms of throughput and up to a factor of five in terms of energy  ...  While FPGAs have shown admirable throughput and energy-efficiency for data processing tasks, developing FPGA accelerators requires a sophisticated hardware design and expensive manual tuning by an expert  ...  ACKNOWLEDGMENTS This work has received funding by the German Ministry for Education and Research as BIFOLD -Berlin Institute for the Foundations of Learning and Data (01IS18025A and 01IS18037A) and Software  ... 
doi:10.5555/3430915.3442428 dblp:journals/pvldb/KieferPBM20 fatcat:dxkoqtxm5bb4bb5k2ix5o7r5cq
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