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VGA—sign choices for a new video subsystem
1988
IBM Systems Journal
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With this ap- proach, a major portion of the design was verified,
THOMPSON
191
The Micro Channel’ interface
he design of the Personal System/2® (PS/2® Models
50, 60, and 80 introduced a new I/O structure ...
The ps/2 systems as a family have been designed to meet the needs of the business and consumer applications, both now and in the future. ...
doi:10.1147/sj.272.0185
fatcat:cezkvuv4yjfhphcwl5nrtaiyf4
The upgraded readout system of the MAGIC telescopes
2012
2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC)
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Finally, the data are sent through an S-LINK optical interface to a single computer. ...
The Domino samplers are integrated in the newly designed mezzanines which equip a set of fourteen multi-purpose PULSAR boards. ...
The support of the German BMBF and MPG, the Italian INFN and Spanish MCINN is gratefully acknowledged. ...
doi:10.1109/nssmic.2012.6551440
fatcat:ddtdqqpcnbdzlaegnfk5od7hpm
The readout system of the MAGIC-II Cherenkov Telescope
[article]
2009
arXiv
pre-print
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Finally, the data are sent through an S-LINK optical interface to a single computer. ...
The Domino samplers are integrated in the newly designed mezzanines which equip a set of fourteen multi-purpose PULSAR boards. ...
The support of the German BMBF and MPG, the Italian INFN and Spanish MCINN is gratefully acknowledged. ...
arXiv:0907.0466v1
fatcat:ymadnbhhyff6pbnb3i4hkz6c3m
Page 740 of SMPTE Motion Imaging Journal Vol. 103, Issue 11
[page]
1994
SMPTE Motion Imaging Journal
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Computer graphics version of TSS theater.
¢ Graphic presentation of the TSS system operations.
* Settings and testing of the TSS processor. ...
JBL Technical Guideline Cinema Sound System Manual, PS 090-0, 1990.
Stanojevic, T., and M. Cipranic, “The Total Surround Sound System,” 86th AES Convention, Hamburg, March 1989.
——., and G. ...
The WaveDAQ integrated Trigger and Data Acquisition System for the MEG II experiment
[article]
2018
arXiv
pre-print
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The WaveDAQ is a newly-designed digitization Trigger and Data AcQuisition system (TDAQ) allowing Multi-gigasample waveform recording on a large amount of channels (up to 16384) by using the DRS4 analog ...
This system has been designed for the MEG experiment upgrade but also proved to be highly scalable and already found other applications. ...
have been measured to be of the order of 10 ps and have proved to be stable over a few month period. ...
arXiv:1806.09218v1
fatcat:j54snpnuqrfllmnhgexruwyk3u
First Measurements on the Timespot1 ASIC: a Fast-Timing, High-Rate Pixel-Matrix Front-End
[article]
2022
arXiv
pre-print
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Targeted to space-time tracking applications in High Energy Physics experiments, the system aims to achieve a time resolution of 30 ps or better at a maximum event rate of 3 MHz per channel with a Data ...
The presented results include a description of the ASIC operation and a first characterization of its performance in terms of time resolution. ...
The board also interfaces the ASIC with FPGA via QTH connector for data IO and provides the system clock via SMA connectors. ...
arXiv:2201.13138v1
fatcat:5qkxsf7n3zdinh7jvcglvjzszu
Microcontroller-based Data Acquisition Device for Process Control and Monitoring Applications
[chapter]
2010
Data Acquisition
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Verification and results Designed device was tested on laboratory model of heating plant system with three temperature measurement channels with unified analog outputs 0 -10 V and two digital input channels ...
From the educational point of view it therefore appears to be useful to acquaint students with a laboratory model of this type of a system. ...
doi:10.5772/10455
fatcat:hlg6pmyibncdnd5f4ap6ccu32e
Page 27 of Journal of Research and Practice in Information Technology Vol. 7, Issue 1
[page]
1975
Journal of Research and Practice in Information Technology
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This system is capable of scanning a picture digitally and recording the optical density of the image with a repeatable accuracy of better than 1%. ...
Image Recording and Display
(a) Optics
SCANNER
—___2ense = +5 neo “XS cpu “ps ] png eo i
Ane Fog
Analogue Computer
Digital Computer
(b) Connection to Hybrid computer Figure 1 Image Scanner
picture is sampled ...
A Software-Defined Spaceborne GNSS Receiver
2018
Zenodo
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The presented approach takes advantage of the flexibility of software-defined radio technology and the forthcoming availability of radiationhardened, space-certified Systems-on-Module to implement a fully ...
This paper reports the design, proof-of-concept implementation and preliminary performance assessment of a lowcost, software-defined spaceborne GNSS receiver. ...
The PS is composed of a dual-core ARM Cortex-A9 MP-Core clocked up to 800 MHz. The on-board PS memory consists of a 1 GB DDR 3 and 256 Mb QSPI memory to store the FPGA firmware if required. ...
doi:10.5281/zenodo.2539211
fatcat:uuptrroyffhuhhsljawwvlgvi4
Page 250 of SMPTE Motion Imaging Journal Vol. 101, Issue 4
[page]
1992
SMPTE Motion Imaging Journal
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The precise size and position of the selected aspect is repeatable by micro- computer control. The new preamplifier technology and a 4:4:4 store provide full bandwidth in all channels. ...
The V2000 Array Router Control System is designed to be intercon- nected over an ethernet system. ...
Design of the Compact Processing Module for the ATLAS Tile Calorimeter
[article]
2020
arXiv
pre-print
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, and data transmission to the TDAQ interface (TDAQi). ...
Triggered data is transmitted through a FULL-mode link to the ATLAS TDAQ system via the FELIX network. ...
and time for each PMT channel to the High-Level Trigger system at a maximum average trigger rate of 100 kHz. ...
arXiv:2011.02684v1
fatcat:ecvcwcbqufb5rjjn4zuvp44bmm
Design of the Compact Processing Module for the ATLAS Tile Calorimeter
2021
IEEE Transactions on Nuclear Science
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, and data transmission to the TDAQ interface (TDAQi). ...
Triggered data is transmitted through a FULL-mode link to the ATLAS TDAQ system via the FELIX network. ...
The Tile Computer on Module (TileCoM): This board is a System-on-Chip-based board which permits remote configuration and monitoring of the on-detector and offdetector readout systems and interfaces with ...
doi:10.1109/tns.2021.3085490
fatcat:oo57w7ily5ahlmazfcr56l3bja
Test electronics for a multi-gbps optical packet switching network
2006
2006 8th Electronics Packaging Technology Conference
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In this paper we present the design and performance characteristics for a custom test system developed to characterize a DWDM optically-routed packet switching network (called "Data Vortex"). ...
The existing demonstration system supports aggregate data rates of 20 to 32 Gbps using 8 optical payload wavelengths each running at 2.5-4.0 Gbps. ...
This DLC, in conjunction with an addon card not pictured, allows for the interconnection of the board to a PCIexpress expansion port on a personal computer. ...
doi:10.1109/eptc.2006.342745
fatcat:kve5li4ty5hdxet4fyc7iskgm4
Molecular Dynamics Simulation of a Synthetic Ion Channel
1998
Biophysical Journal
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The total dipole moment and the inertia tensor of the peptide bundle have been calculated and reveal slow (300 ps) collective oscillatory motions. ...
In the present simulation, the channel was initially assembled as a parallel bundle in the octane portion of a phase-separated water/octane system, which provided a membrane-mimetic environment. ...
We used a single Nosé-Hoover chain of length 3, and the frequency factor of the chain was chosen to be 2 ps Ϫ1 . ...
doi:10.1016/s0006-3495(98)77761-6
pmid:9449304
pmcid:PMC1299356
fatcat:kgmbiq5bm5bvvkgp625a26puue
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network
2007
2007 IEEE International Test Conference
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This paper presents the design and performance characteristics of a system designed to interface between a PCI Express port and an optical packet switched network as well as provide inline test capability ...
Testing options include loopback self-test, data synthesis and substitution in-line with or in place of system data, and variable channel-to-channel skew. ...
PCI Express Interface Card A picture of the PCI Express interface card is shown in The PHY greatly reduces the design complexity required for a system to interface to PCI Express, performing data and clock ...
doi:10.1109/test.2007.4437623
dblp:conf/itc/GrayLKB07
fatcat:7n63mif4bbacxoi44osx6tknyi
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