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A method to derive application-specific embedded processing cores

Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications.  ...  We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.  ...  Local Constant Tables Constant values are often used in the microcode, to enable immediate addressing modes and compare operations.  ... 
doi:10.1145/334012.334029 dblp:conf/codes/HebertKS00 fatcat:ud5bk6hxk5ftxevtg3bmufcuvy

Intermediate representations for controllers in chip generators

K Kelley, M Wachs, A Danowitz, P Stevenson, S Richardon, M Horowitz
2011 2011 Design, Automation & Test in Europe  
Creating parameterized "chip generators" has been proposed as one way to decrease chip NRE costs.  ...  The most common approach is to create a microcoded engine as the controller, which offers flexibility through programmable table-based lookup functions.  ...  ACKNOWLEDGEMENT The authors would like to thank Amin Firoozshahian and Alex Solomatnikov for their help and support.  ... 
doi:10.1109/date.2011.5763225 dblp:conf/date/KelleyWDSRH11 fatcat:v4h7wufqqzhn3gsfyojfrhhm7y

Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping

Nathan Clark, Amir Hormati, Sami Yehia, Scott Mahlke, Krisztian Flautner
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
We provide a detailed description of changes to a compilation framework and processor pipeline needed to support this abstraction.  ...  With larger hardware budgets and more demands for performance, SIMD accelerators evolve with both larger data widths and increased functionality with each new generation.  ...  There are two phases necessary in decoupling SIMD accelerators from the processor's instruction set. First, an offline phase takes SIMD instructions and maps them to an equivalent representation.  ... 
doi:10.1109/hpca.2007.346199 dblp:conf/hpca/ClarkHYMF07 fatcat:k7a7acld7fczno64yy6yqunmyi

On Horizontally Microprogrammed Microarchitecture Description Techniques

J.L. Gieser
1982 IEEE Transactions on Software Engineering  
In automatically generating microcode starting from a highlevel source language, a significant issue is the description of the target microengine architecture.  ...  Its objective is to identify the techniques that appear to have the most promise for use in interjecting the target microarchitecture characteristics into the high-level language-to-microcode compilation  ...  Research into global microcode optimization techniques has enjoyed success as well (see, for example, [10] , [11] , and [28] ).  ... 
doi:10.1109/tse.1982.235739 fatcat:fs6oaisf7zgtrgqyli36i6pqaa

The design of an interactive compiler for optimizing microprograms

S. R. Vegdahl
1985 Proceedings of the 18th annual workshop on Microprogramming - MICRO 18  
A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures  ...  Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever  ...  Unfortunately, current technology is unable to deliver compilers that generate code with optimizations that are as efficient and creative as those of an expert microprogrammer [Vegdahl82] .  ... 
doi:10.1145/18927.18919 dblp:conf/micro/Vegdahl85 fatcat:okflbmlaezdnpmjqgu4yzaeu7e

Built-in self-testing of random-access memories

M. Franklin, K.K. Saluja
1990 Computer  
Acknowledgments This work was supported by the University of Wisconsin Graduate Research Committee, an IBM graduate fellowship, and the National Science Foundation under contract MIP 8509194.  ...  We thank the referees for their comments and suggestions, which greatly enhanced the quality of presentation of this work.  ...  Generally, as the memory size increases, the number of arrays increases, with the size of an array remaining more or less constant.  ... 
doi:10.1109/2.58236 fatcat:bt6vpurmrrbslh24hzoomqjjem

The design of an interactive compiler for optimizing microprograms

S. R. Vegdahl
1985 ACM SIGMICRO Newsletter  
A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures  ...  Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever  ...  Unfortunately, current technology is unable to deliver compilers that generate code with optimizations that are as efficient and creative as those of an expert microprogrammer [Vegdahl82] .  ... 
doi:10.1145/18906.18919 fatcat:bmd7iqazjrh33lbd5k6xmsiyua

apeNEXT: A Multi-TFlops computer for elementary particle physics [chapter]

F. Bodin, Ph. Boucaud, N. Cabibbo, F. Di Carlo, R. De Pietri, F. Di Renzo, H. Kaldass, A. Lonardo, M. Lukyanov, S. de Luca, J. Micheli, V. Morenas (+9 others)
2004 Advances in Parallel Computing  
Like previous APE machines, the new supercomputer is completely custom designed and is specifically optimized for simulating the theory of strong interactions, quantum chromodynamics (QCD).  ...  the CPU requirements as a function of the relevant physical parameters are given in [3] .  ...  Errico (INFN) for his important work in the early phases of the project, and A. Agarwal (DESY/Zeuthen) and T. Giorgino (INFN) for their contributions.  ... 
doi:10.1016/s0927-5452(04)80047-9 fatcat:lfdzjv3spjdxhdjzo3jvlbiofa

Pangaea

Henry Wong, Hong Wang, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham Chinya, Ankur Khandelwal Groen, Hong Jiang
2008 Proceedings of the 17th international conference on Parallel architectures and compilation techniques - PACT '08  
We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU.  ...  Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators.  ...  In addition, we would like to thank the anonymous reviewers whose valuable feedback has helped the authors greatly improve the quality of this paper.  ... 
doi:10.1145/1454115.1454125 dblp:conf/IEEEpact/WongBSACWCGJW08 fatcat:p37zbpaobza7pngzkxogk37fyy

The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development

W. Gellerich, T. Hendel, R. Land, H. Lehmann, M. Mueller, P. H. Oden, H. Penner
2004 IBM Journal of Research and Development  
The section that follows is about the project itself and gives details about the GNU compiler collection (GCC), and in particular the PL8 compiler front end.  ...  The GNU compiler collection (GCC) (GNU is a freeware UNIX ᭨ -like operating system) has been used to translate those parts of firmware written in C for some years and has also proved successful in compiling  ...  Most of the compiler error messages and warnings are generated by this phase. The source code analysis results in an internal program representation.  ... 
doi:10.1147/rd.483.0543 fatcat:wgyffa5rwrbwhcnb5nal2y7xdm

A low power architecture for embedded perception

Binu Mathew, Al Davis, Mike Parker
2004 Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '04  
This paper introduces a VLIW perception processor which uses a combination of clustered function units, compiler controlled dataflow and compiler controlled clock-gating in conjunction with a scratch-pad  ...  The energydelay product of a 0.13µ implementation of this architecture is compared against ASICs and general purpose processors.  ...  In the initial phase of this research, an ASIC coprocessor for one of the dominant phases of the CMU Sphinx speech recognition system was investigated [17] .  ... 
doi:10.1145/1023833.1023842 dblp:conf/cases/MathewDP04 fatcat:kuedf5evtjbkvll2jkpmrs2c7e

OpenQASM 3: A broader and deeper quantum assembly language [article]

Andrew W. Cross, Ali Javadi-Abhari, Thomas Alexander, Niel de Beaudrap, Lev S. Bishop, Steven Heidel, Colm A. Ryan, John Smolin, Jay M. Gambetta, Blake R. Johnson
2021 arXiv   pre-print
These new language features create a multi-level intermediate representation for circuit development and optimization, as well as control sequence implementation for calibration, characterization, and  ...  Since the near-time domain is adequately described by existing programming frameworks, we choose in OpenQASM 3 to focus on the real-time domain, which must be more tightly coupled to the execution of quantum  ...  Karalekas, Moritz Kirste, Kevin Krsulich, Andrew Landahl, Prakash Murali, Salva de la Puente, Kenneth Rudinger, Prasahnt Sivarajah, Zachary Schoenfeld, Yunong Shi, Stefan Teleman, Ntwali Bashinge Toussaint, and  ... 
arXiv:2104.14722v1 fatcat:qzffzictazcl3or6z7eqgtilnm

The apeNEXT project

F. Bodin, P. Boucaud, N. Cabibbo, F. Calvayrac, M. Della Morte, R. De Pietri, P. De Riso, F. Di Carlo, F. Di Renzo, W. Errico, R. Frezzotti, U. Gensch (+22 others)
2002 Nuclear Physics B - Proceedings Supplements  
APENEXT is a new generation APE processor, optimized for LGT simulations.  ...  The project follows the basic ideas of previous APE machines and develops simple and cheap parallel systems with multi T-Flops processing power.  ...  Errico for his important work in the early phases of the project, and A. Agarwal, T. Giorgino and M. Lukyanov for their contributions.  ... 
doi:10.1016/s0920-5632(01)01656-5 fatcat:sdxvfkfvhfdvpebuzuo4cfodtm

The apeNEXT project (Status report) [article]

F. Bodin, Ph. Boucaud, J. Micheli, O. Pene, N. Cabibbo, F. Di Carlo, A. Lonardo, S. de Luca, F. Rapuano, D. Rossetti, P. Vicini, R. De Pietri, F. Di Renzo (+8 others)
2003 arXiv   pre-print
We discuss the machine design, report on benchmarks, and give an overview on the status of the software development.  ...  Aim of this project is the development of the next generation of APE machines which will provide multi-teraflop computing power.  ...  Errico for his important work in the early phases of the project, and A. Agarwal, T. Giorgino and M. Lukyanov for their contributions.  ... 
arXiv:hep-lat/0306018v2 fatcat:yprbutq3cvhcjdqrcdxajvqb7m

Compilation for a high-performance systolic array

Thomas Gross, Monica S. Lam
1986 Proceedings of the 1986 SIGPLAN symposium on Compiler contruction - SIGPLAN '86  
Programming in W2 (the language accepted by the compiler) is orders of magnitude easier than coding in microcode, the only alternative available previously.  ...  This compiler enhances the uscfulncss of Warp significantly and allows application programmers to code substantial algorithms.  ...  Mosur, and P. Steenkiste, who all helped with the implementation of this compiler. H. Enderton, B. Siegel). and J. Webb are the first users of the compiler and suffered through the first releasea.  ... 
doi:10.1145/12276.13314 dblp:conf/sigplan/GrossL86 fatcat:zleptouad5cafksmztyav4zhxq
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