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Persistent Owicki-Gries reasoning: a program logic for reasoning about persistent programs on Intel-x86

Azalea Raad, Ori Lahav, Viktor Vafeiadis
2020 Proceedings of the ACM on Programming Languages (PACMPL)  
We prove the soundness of POG over the recent Intel-x86 model, which formalises the out-of-order persistence of memory stores and the semantics of the Intel cache line flush instructions.  ...  To address this, we study the verification of NVM programs, and present Persistent Owicki-Gries (POG), the first program logic for reasoning about such programs.  ...  Ori Lahav was supported by the Israel Science Foundation (grant number 5166651), by Len Blavatnik and the Blavatnik Family foundation, and by the Alon Young Faculty Fellowship.  ... 
doi:10.1145/3428219 fatcat:rddaqrnf3ncyvfvtykt2f4lm2i

Creating portable and efficient packet processing applications

Olivier Morandi, Fulvio Risso, Pierluigi Rolando, Silvio Valenti, Paolo Veglia
2011 Design automation for embedded systems  
a wide range of applications), software portability across heterogeneous network processor architectures, and efficiency of the generated code, often exceeding the one obtained using state-of-the-art compilers  ...  However, software development for these platforms is traditionally cumbersome due both to the lack of adequate programming abstractions and to the impossibility of reusing the same software on different  ...  ) colleagues who participated in the early days of this project, particularly Mario Baldi, Loris Degioanni and Gianluca Varenni who were part of the group of people who started the NetVM project back in  ... 
doi:10.1007/s10617-011-9072-8 fatcat:2fnuiaefyba25bxovdyi4zf46q

Design and implementation of a framework for creating portable and efficient packet-processing applications

Olivier Morandi, Fulvio Risso, Silvio Valenti, Paolo Veglia
2008 Proceedings of the 7th ACM international conference on Embedded software - EMSOFT '08  
Our implementation supports three different target architectures: one with a general purpose processor (Intel x86), one with a multi-core network processor (Cavium Octeon) and one with a systolic-array  ...  This paper describes the architecture of a runtime environment and a compiler infrastructure for the Network Virtual Machine (NetVM), showing that the portability of packetprocessing programs can be achieved  ...  ACKNOWLEDGEMENTS The authors wish to thank Marco Bergero and Pierluigi Rolando for the contribution they have given respectively in the development of the NetVM runtime environment and of the optimization  ... 
doi:10.1145/1450058.1450091 dblp:conf/emsoft/MorandiRVV08 fatcat:jleeuytcufafvllqfdkqbu7qfy

SoK: Hardware Security Support for Trustworthy Execution [article]

Lianying Zhao, He Shuang, Shengjie Xu, Wei Huang, Rongzhen Cui, Pushkar Bettadpur, David Lie
2019 arXiv   pre-print
In recent years, there have emerged many new hardware mechanisms for improving the security of our computer systems.  ...  In this paper, we systematize these approaches through the lens of abstraction. Abstraction is key to computing systems, and the interface between hardware and software contains many abstractions.  ...  TEEs across architectures In light of the importance of TEEs in establishing (the chain of) trust for a computing platform, we review the presence and positioning of TEEs across mainstream architectures  ... 
arXiv:1910.04957v1 fatcat:5luczjg34ve67nm73xso5xhzx4

Follow the WhiteRabbit: Towards Consolidation of On-the-Fly Virtualization and Virtual Machine Introspection [chapter]

Sergej Proskurin, Julian Kirsch, Apostolis Zarras
2018 IFIP Advances in Information and Communication Technology  
Our prototype employs Intel as well as ARM virtualization extensions to take over control of a running Linux system.  ...  To benefit from this ability, a VMI-aware Virtual Machine Monitor (VMM) must be set up in advance underneath the target system; a constraint for the massive application of VMI.  ...  We validated our kernel module based prototype on Linux running on-top of Intel x86-64.  ... 
doi:10.1007/978-3-319-99828-2_19 fatcat:5zcbqng5l5c53cz7jayzgzfmjq

Reverse Engineering x86 Processor Microcode [article]

Philipp Koppe and Benjamin Kollenda and Marc Fyrbiak and Christian Kison and Robert Gawlik and Christof Paar and Thorsten Holz
2019 arXiv   pre-print
In this paper, we reverse engineer the microcode semantics and inner workings of its update mechanism of conventional COTS CPUs on the example of AMD's K8 and K10 microarchitectures.  ...  We describe the microcode semantics and additionally present a set of microprograms that demonstrate the possibilities offered by this technology.  ...  Part of this work was supported by the European Research Responsible Disclosure We contacted AMD in a responsible disclosure process more than 90 days prior to publication and provided detailed information  ... 
arXiv:1910.00948v1 fatcat:lajfppfs55f2vd3mj4wcat77ly

Processing Panorama Video in Real-time

Håkon Kvale Stensland, Vamsidhar Reddy Gaddam, Marius Tennøe, Espen Helgedagsrud, Mikkel Næss, Henrik Kjus Alstad, Carsten Griwodz, Pål Halvorsen, Dag Johansen
2014 International Journal of Semantic Computing (IJSC)  
Processor architectures have been evolving quickly since the introduction of the central processing unit.  ...  The P2G framework is designed for multimedia workloads and supports heterogeneous architectures. To demonstrate the feasibility of the framework, we construct a proof-of-concept implementation.  ...  The Haswell Architecture The latest x86 architecture from Intel is called Haswell [104] .  ... 
doi:10.1142/s1793351x14400054 fatcat:hafewx3ekrcfpat2osb67fjugi

Model-based approach for semantic-driven deployment of containerized applications to support future internet services and architectures

Nenad Petrovic
2019 Serbian Journal of Electrical Engineering  
In this paper, a model-based framework for automated, semantic-driven (re-)deployment of containerized applications is presented, leveraging the synergy of Virtual Network Functions (VNFs) and SDN, tackling  ...  Due to increasing number of connected Internet of Things (IoT) devices, enormous amount of data needs to be transmitted to the Cloud for processing, while the network is becoming Cloud computing's bottleneck  ...  The later also includes scenarios of computation task movement between devices of different computing architectures in IoT systems (x86 and ARM), supporting the scenarios of Edge computing.  ... 
doi:10.2298/sjee1901021p fatcat:zipfne4jqfbzje37bmauofi5lq

A Verification-Based Approach to Memory Fence Insertion in Relaxed Memory Systems [chapter]

Alexander Linden, Pierre Wolper
2011 Lecture Notes in Computer Science  
Specifically, it considers the TSO (Total Store Order) relaxation, which corresponds to the use of store buffers, and its extension x86-TSO, which in addition allows synchronization and lock operations  ...  Its starting point is a program that is correct for the usual sequential consistency memory model, but that might be incorrect under x86-TSO.  ...  In spite of its name, x86-TSO is not an exact model of a given architecture, but is an abstract programmer's model that covers the documented behaviors of a wide range of processors.  ... 
doi:10.1007/978-3-642-22306-8_10 fatcat:7emfy7wco5e5ja3xzxfs7vlzce

Welcome to the opportunities of binary translation

E.R. Altman, D. Kaeli, Y. Sheffer
2000 Computer  
Translated applications can be cached in persistent storage but must preserve the normal semantics of an executable file.  ...  For example, if the legacy architecture has special seg- Collaborative Profiling Youfeng Wu, Intel To accelerate performance, profile information should be aggregated and ready for use in optimization  ...  We thank the workshop's program committee members and the organizers of PACT 99. Erik R. Altman  ... 
doi:10.1109/2.825694 fatcat:2c3imcq2evbaxjsw5dqbumavy4

Virtualization Technologies and Cloud Security: advantages, issues, and perspectives [article]

Roberto Di Pietro, Flavio Lombardi
2018 arXiv   pre-print
The objective of this paper is to shed light on current virtualization technology and its evolution from the point of view of security, having as an objective its applications to the Cloud setting.  ...  These features provide an explanation, although partial, of why virtualization has been an enabler for the flourishing of cloud services.  ...  Execution Rings for the x86 64 Architecture.  ... 
arXiv:1807.11016v2 fatcat:i724ystx2zcqtgm2aq7bkkkedm

Co-processor-based Behavior Monitoring

Ronny Chevalier, Maugan Villatel, David Plaquin, Guillaume Hiet
2017 Proceedings of the 33rd Annual Computer Security Applications Conference on - ACSAC 2017  
, less than the 150 $\mu$s threshold defined by Intel).  ...  We evaluate the ability of our approach to detect state-of-the-art attacks and its runtime execution overhead by simulating an x86 system coupled with an ARM Cortex A5 co-processor.  ...  ACKNOWLEDGMENTS The authors would like to thank and acknowledge the contribution of the following people (in alphabetical order) for their helpful comments, technical discussions, feedback and proofing  ... 
doi:10.1145/3134600.3134622 dblp:conf/acsac/ChevalierVPH17 fatcat:jizvvr647rgmpfbvc7xp7x7rsu

Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA

Maria Mushtaq, Muhammad Asim Mukhtar, Vianney Lapotre, Muhammad Khurram Bhatti, Guy Gogniat
2020 Information Systems  
We identify leakages at different levels of the Intel x86 cache hierarchy that help narrow down major attack possibilities in caches. • We provide a taxonomy of leakage channels, their classification,  ...  x86).  ...  ACKNOWLEDGMENTS This work was partially supported by the Pak-France joint research project e-health.  ... 
doi:10.1016/j.is.2020.101524 fatcat:odegutokz5hrhmwsznlc7px6qm

On the Performance of Intel SGX

ChongChong Zhao, Daniyaer Saifuding, Hongliang Tian, Yong Zhang, ChunXiao Xing
2016 2016 13th Web Information Systems and Applications Conference (WISA)  
One cornerstone of computer security is hardware-based isolation mechanisms, among which an emerging technology named Intel Software Guard Extensions (SGX) offers arguably the strongest security on x86  ...  Intel SGX enables user-level code to create trusted memory regions named enclaves, which are isolated from the rest of the system, including privileged system software.  ...  To provide a stronger security than existing hardware-based isolation mechanisms, Intel Software Guard Extensions (SGX) [15] is introduced to x86 architecture.  ... 
doi:10.1109/wisa.2016.45 dblp:conf/IEEEwisa/ZhaoSTZX16 fatcat:dusw2rgzs5f3hezvkpuww7lroy

Taming x86-TSO Persistency (Extended Version) [article]

Artem Khyzha, Ori Lahav
2020 arXiv   pre-print
We study the formal semantics of non-volatile memory in the x86-TSO architecture.  ...  The latter provides a novel model that is much closer to common developers' understanding of persistency semantics.  ...  The second author was also supported by the Alon Young Faculty Fellowship.  ... 
arXiv:2010.13593v2 fatcat:swpqdfnd7jghxh3xhtyssmazbu
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