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Performance-driven analog placement considering boundary constraint

Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands.  ...  This phenomenon can not be identified by a cost function, which only considers placement area and total wire length.  ...  We call it symmetry-island boundary constraint and consider it in analog and mixed-signal placement.  ... 
doi:10.1145/1837274.1837348 dblp:conf/dac/LinLHC10 fatcat:azlcfyjtaza35ju3mlmmc2ozie

Thermal-Driven Analog Placement Considering Device Matching

Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and  ...  With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices  ...  Section 3 presents our thermal-driven analog placement to generate the desired thermal profile based on the placement configuration while considering both symmetry and common-centroid constraints.  ... 
doi:10.1109/tcad.2010.2097308 fatcat:gkjqb5a3ova3ncldngegl2nsuu

Thermal-driven analog placement considering device matching

Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
We then propose a thermal-driven analog placement methodology to achieve the desired thermal profile and to consider the best device matching under the thermal profile while satisfying the symmetry and  ...  With the thermal effect, improper analog placements may degrade circuit performance because the thermal impact from power devices can affect electrical characteristics of the thermally-sensitive devices  ...  Section 3 presents our thermal-driven analog placement to generate the desired thermal profile based on the placement configuration while considering both symmetry and common-centroid constraints.  ... 
doi:10.1145/1629911.1630064 dblp:conf/dac/LinZWC09 fatcat:vv44ym5dj5h5paguasga7iunfi

A constraint-driven methodology for placement of analog and mixed-signal integrated circuits

Ammar Nassaj, Jens Lienig, Goran Jerke
2008 2008 15th IEEE International Conference on Electronics, Circuits and Systems  
Unlike the optimization engines known so far, our implementation is driven not only by the placement objectives, but also by the adaptively weighted constraints.  ...  Stringent constraints that must be considered simultaneously are a major reason why layout design is often not automated.  ...  This allows intelligently searching the solution space by considering the ranges and boundaries of the various constraints in order to prevent constraint violations.  ... 
doi:10.1109/icecs.2008.4674967 dblp:conf/icecsys/NassajLJ08 fatcat:uvqvzhfuvrbnled2hhfxtrzqli

A new methodology for constraint-driven layout design of analog circuits

Ammar Nassaj, Jens Lienig, Goran Jerke
2009 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)  
The resulting comprehensive constraint-driven design approach allows defining and verifying the analog layout constraints by transforming them between the different design domains.  ...  Layout design of analog integrated circuits suffers from a lack of automation due to the multitude of complex design constraints.  ...  It considers symmetry, device abutment and merging constraints. In [4] , performance-driven layout techniques are presented.  ... 
doi:10.1109/icecs.2009.5410838 dblp:conf/icecsys/NassajLJ09 fatcat:zkfven236zac7e5wujfr4kxmeu

Fast and Effective Placement Refinement for Routability

Yanheng Zhang, Chris Chu
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
CROP consists of a congestion-driven module shifting technique and a congestion-driven detailed placement (CDDP) technique.  ...  In order to better analyze its performance, the ISPD-GR benchmark suite (ISPD05/06 derived global routing benchmarks) with FM modes is developed.  ...  In analog designs, there are design constraints that need be respected for macros, such as mirroring constraints (e.g., two blocks are the mutually viewed images for a fixed axis), alignment constraint  ... 
doi:10.1109/tvlsi.2012.2214408 fatcat:tun2fpmlr5c6lh27q7y3fdsnqa

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts

Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
Parasitic effects are extremely significant for the performance of analog and RF integrated circuits.  ...  Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints  ...  These present a great challenge for analog layout automation. Malvasi et al. proposed the first fully integrated constraint-driven analog layout system [3] .  ... 
doi:10.1145/1233501.1233570 dblp:conf/iccad/JangkrajarngZBKS06 fatcat:xf5dahmkordxvnhe6rle3twp2i

Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts

Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-j. Shi
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
Parasitic effects are extremely significant for the performance of analog and RF integrated circuits.  ...  Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints  ...  These present a great challenge for analog layout automation. Malvasi et al. proposed the first fully integrated constraint-driven analog layout system [3] .  ... 
doi:10.1109/iccad.2006.320056 fatcat:zdazrlmjtrgs7e665sqwan2vfy

Constraint-Based Layout-Driven Sizing of Analog Circuits

Husni Habal, Helmut Graeb
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The type and number of placement constraints considered during placement will affect the electrical circuit performance values as demonstrated in [ESGS10, ESL + 11].  ...  placement is considered to have failed.  ... 
doi:10.1109/tcad.2011.2158732 fatcat:schj7wh4fnfazepnii5cgywpfa

Analog placement with symmetry and other placement constraints

Yiu-Cheong Tam, Evangeline F. Y. Young, Chris Chu
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously.  ...  The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously.  ...  Since most of the previous works on analog placement do not consider other general placement constraints, we only have symmetry constraints in the first set of data.  ... 
doi:10.1145/1233501.1233571 dblp:conf/iccad/TamYC06 fatcat:op2ojk7dinc5lde5iljqrttvy4

Analog Placement with Symmetry and Other Placement Constraints

Yiu-cheong Tam, Evangeline Young, Chris Chu
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper addresses this device-level placement problem for analog circuits and our approach can handle symmetry constraint and other placement constraints simultaneously.  ...  The problem of placing devices with symmetry constraint has been extensively studied but none of the previous works has considered symmetry constraint with other placement constraints simultaneously.  ...  Since most of the previous works on analog placement do not consider other general placement constraints, we only have symmetry constraints in the first set of data.  ... 
doi:10.1109/iccad.2006.320057 fatcat:p4vxrcgrs5hstfber5fiasz6nu

Placement constraints in floorplan design

E.F.Y. Young, C.C.N. Chu, M.L. Ho
2004 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we will present a unified method to handle all of them simultaneously, including preplace constraint, range constraint, boundary constraint, alignment, abutment and clustering, etc., in  ...  There are several previous works [3], [5], [7], [8], [10], [12]-[14] focusing on some particular kinds of placement constraints.  ...  He received the IEEE TCAD best paper award at 1999 for his work in performance-driven interconnect optimization.  ... 
doi:10.1109/tvlsi.2004.830915 fatcat:btnh3x2hyzcwdbull5p7ttnk5a

Hierarchical Placement with Layout Constraints [chapter]

Mark Po-Hung Lin, Yao-Wen Chang
2010 Analog Layout Synthesis  
In analog layout design, devices are required to be placed with matching, symmetry, and proximity constraints to reduce parasitic coupling effects and improve circuit performance.  ...  This chapter first introduces the hierarchical constraints induced by circuit and layout design hierarchies, and then presents a hierarchical placement approach to better consider these hierarchical constraints  ...  Table 2 .2 compares aforementioned analog placement approaches considering symmetry constraints based on topological floorplan representations.  ... 
doi:10.1007/978-1-4419-6932-3_2 fatcat:enclmtlcy5al5bie2w3x5qgrpa

A technology-independent methodology of placement generation for analog circuit

Wai-Chee Wong, P.C.H. Chan, Wai-On Law
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented.  ...  The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration.  ...  Analog constraints such as device matching, performance degradation related to parasitic devices and pin locations can be handled by the cost function successfully.  ... 
doi:10.1109/aspdac.1999.759980 dblp:conf/aspdac/WongCL99 fatcat:7lsd22cimjbjppssjxjjfd3umi

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren
2022 Proceedings of the 2022 International Symposium on Physical Design  
AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design constraints while adhering to typical FinFET layout styles.  ...  Despite continuous efforts in layout automation for full-custom circuits, including analog/mixed-signal (AMS) designs, automated layout tools have not yet been widely adopted in current industrial full-custom  ...  Figure 3 (b) a short connection between boundary pins caused by insufficient placement constraints.  ... 
doi:10.1145/3505170.3511044 fatcat:tovuba5ac5hj7msttbdgouf7ku
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