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Performance-directed retiming for FPGAs using post-placement delay information

U. Seidl, K. Eckl, F. Johannes
2003 Design, Automation and Test in Europe Conference and Exhibition  
Many existing performance-directed retiming methods use simple delay models which either neglect routing delays or use inaccurate delay estimations.  ...  Our retiming technique uses delay information extracted from a fully placed and routed design and takes account of register timing requirements.  ...  Singh and Brown [14] apply the vpr tool to FPGA designs to determine post placement routing delay information.  ... 
doi:10.1109/date.2003.1253700 fatcat:wuqhkgabrvaoxajpogxdff76oa

Post-placement C-slow retiming for the xilinx virtex FPGA

Nicholas Weaver, Yury Markovskiy, Yatish Patel, John Wawrzynek
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs.  ...  For some parameters, throughput is effectively doubled.  ...  The simplified FPGA model used has a logic block where the the flip flop can not be used independantly of the LUT, constraining the ability of post placement retiming to allocate new registers.  ... 
doi:10.1145/611843.611845 fatcat:qbvnznximnhypmnexbxdzssuvi

Post-placement C-slow retiming for the xilinx virtex FPGA

Nicholas Weaver, Yury Markovskiy, Yatish Patel, John Wawrzynek
2003 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays - FPGA '03  
To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs.  ...  For some parameters, throughput is effectively doubled.  ...  The simplified FPGA model used has a logic block where the the flip flop can not be used independantly of the LUT, constraining the ability of post placement retiming to allocate new registers.  ... 
doi:10.1145/611817.611845 dblp:conf/fpga/WeaverMPW03 fatcat:iukxgrr4z5e5fneboffsxwa2cm

Integrated retiming and placement for field programmable gate arrays

Deshanand P. Singh, Stephen D. Brown
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features.  ...  If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect.  ...  It is these cycle-slacks that can be used to inform the placer about which connections are critical, given that we will perform retiming after placement.  ... 
doi:10.1145/503057.503059 fatcat:2tyd7r7mmrarxkpzqcbrrrdvdu

Simultaneous Retiming and Placement for Pipelined Netlists

Ken Eguro, Scott Hauck
2008 2008 16th International Symposium on Field-Programmable Custom Computing Machines  
Our results show that for heavily pipelined applications, this methodology can produce netlists and placements with 1.65x better post-routing critical path delay as compared to the classical approach of  ...  Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architectures and CAD tools: what  ...  However, it is also unclear how useful it might be to try and forward timing information from a previous placement and routing back to the retimer for another run of the CAD tools.  ... 
doi:10.1109/fccm.2008.21 dblp:conf/fccm/EguroH08 fatcat:6jnzvvo3rbbyjc72dfdchc5bwy

Integrated retiming and placement for field programmable gate arrays

Deshanand P. Singh, Stephen D. Brown
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
Specifically, we introduce a post-placement retiming algorithm that understands how to take advantage of FPGA architectural features.  ...  If a circuit is retimed prior to the placement and routing phases of the CAD flow, then it has no information about the delays introduced by the configurable interconnect.  ...  It is these cycle-slacks that can be used to inform the placer about which connections are critical, given that we will perform retiming after placement.  ... 
doi:10.1145/503048.503059 dblp:conf/fpga/SinghB02 fatcat:brccd5kxqrcwvbnnabpomm66aa

Delay budgeting in sequential circuit with application on FPGA placement

Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We then utilize the skew-retiming equivalence relation [9] and retime the circuit. We demonstrate usefulness of our approach in the context of FPGA placement flow.  ...  Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits.  ...  We also apply the FF reduction algorithm at the end of both flows for post-placement optimization. EXPERIMENTAL RESULTS We use MCNC benchmark for our experiments.  ... 
doi:10.1145/775884.775886 fatcat:a6tp2q645bhs5hapgnitsm3sz4

Delay budgeting in sequential circuit with application on FPGA placement

Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003 Proceedings of the 40th conference on Design automation - DAC '03  
We then utilize the skew-retiming equivalence relation [9] and retime the circuit. We demonstrate usefulness of our approach in the context of FPGA placement flow.  ...  Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits.  ...  We also apply the FF reduction algorithm at the end of both flows for post-placement optimization. EXPERIMENTAL RESULTS We use MCNC benchmark for our experiments.  ... 
doi:10.1145/775832.775886 dblp:conf/dac/YehM03 fatcat:arsk5sh3obbl5dm6pn4yqzvobe

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

C.h. Ho, P.h.w. Leong, W. Luk, S.J.E. Wilton, S. Lopez-Buedo
2006 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines  
The standard design flow offered by FPGA and CAD vendors can be used for mapping, placement, routing and retiming of designs with VEBs.  ...  The methodology involves creating dummy elements, called Virtual Embedded blocks (VEBs), in the FPGA to model the size, position and delay of the embedded elements.  ...  Figure 5 . 5 Performance of floating-point bfly benchmark for different FPU delays, with retiming. Table 1.  ... 
doi:10.1109/fccm.2006.71 dblp:conf/fccm/HoLLWL06 fatcat:5ybzjpumcjbrtlvih4hdjwfdri

Incremental physical resynthesis for timing optimization

Peter Suaris, Lungtien Liu, Yuzheng Ding, Nanchi Chou
2004 Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays - FPGA '04  
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations  ...  many types of optimizations including cell repacking, signal rerouting, resource retargeting, and logic restructuring, accompanied by efficient incremental placement, to gradually transform a design via  ...  Combinational logic synthesis for timing optimization involves reduction of path delays, thus also benefits from physical delay information. In [16] , logic duplication is performed after placement.  ... 
doi:10.1145/968280.968296 dblp:conf/fpga/SuarisLDC04 fatcat:haf7g23yxjex5iogzffalc6tne

Multilevel global placement with retiming

Jason Cong, Xin Yuan
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Experimental results show that (i) retiming can improve the performance (delay) by 14% on average when it is applied after placement; (ii) our approach for simultaneous retiming and placement can outperform  ...  In this paper, we present a practical solution for simultaneous retiming and multilevel global placement for performance optimization, based on the theory and algorithms of sequential timing analysis (  ...  In [20] retiming is integrated into a simulated anneal-ing (SA)-based placement for FPGA designs.  ... 
doi:10.1145/775884.775887 fatcat:dowrvt2rjfgvtfcb2njor3prtm

Multilevel global placement with retiming

Jason Cong, Xin Yuan
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Experimental results show that (i) retiming can improve the performance (delay) by 14% on average when it is applied after placement; (ii) our approach for simultaneous retiming and placement can outperform  ...  In this paper, we present a practical solution for simultaneous retiming and multilevel global placement for performance optimization, based on the theory and algorithms of sequential timing analysis (  ...  In [20] retiming is integrated into a simulated anneal-ing (SA)-based placement for FPGA designs.  ... 
doi:10.1145/775832.775887 dblp:conf/dac/CongY03 fatcat:svncxq2caffango7bmqpnioleu

Incremental placement for layout driven optimizations on FPGAs

Deshanand P. Singh, Stephen D. Brown
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
The incremental placement engine assumes that the restructuring algorithms provide a list of new logic elements along with preferred locations for each of these new elements.  ...  Our algorithm considers modern FPGA architectures with clustered logic blocks that have numerous architectural constraints.  ...  As reported in [6] , the application of post-placement retiming in conjunction with ICP results in a 22% increase in operating frequency in comparison to preplacement retiming.  ... 
doi:10.1145/774572.774683 dblp:conf/iccad/SinghB02 fatcat:ioual4yf5jfwni7jv6b5kpsdpe

Latch-Based Performance Optimization for FPGAs

Bill Teng, Jason H. Anderson
2011 2011 21st International Conference on Field Programmable Logic and Applications  
We explore using pulsed latches for timing optimization -a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle.  ...  such as clock skew and retiming.  ...  CONCLUSIONS AND FUTURE WORK In this paper, we considered performance optimization using pulsed latches for FPGAs.  ... 
doi:10.1109/fpl.2011.21 dblp:conf/fpl/TengA11 fatcat:tz5tpxkxfvf2tcmyt6bfsvqhxi

Combined instruction and loop parallelism in array synthesis for FPGAs

Steven Derrien, Sanjay Rajopadhye, Susmita Sur Kolay
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
They are then moved into the pe data-path using standard commerecial circuit retimers. Our experiments (based on performance estimates after place-and-route) have been very encouraging.  ...  For a number of examples we have seen dramatic performance improvements: speed increases of an order of magnitude with relatively little (always less than 100%) area overhead.  ...  by exploiting placement information.  ... 
doi:10.1145/500001.500039 fatcat:32wlshgaizgqddpbitp4lh4xdy
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