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Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse

Ho Young Kim, Tag Gon Kim
2005 Proceedings. 42nd Design Automation Conference, 2005.  
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique.  ...  Since exploration of an optimal processor is a timeconsuming task due to large design space, fast evaluation methodology for an architecture is crucial.  ...  Early pipeline evaluation technique was proposed for fast behavioral simulation [5] .  ... 
doi:10.1109/dac.2005.193829 fatcat:apo2rrjhdnbetpv5qhjnexm6qu

Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse

Ho Young Kim, Tag Gon Kim
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique.  ...  Since exploration of an optimal processor is a timeconsuming task due to large design space, fast evaluation methodology for an architecture is crucial.  ...  Early pipeline evaluation technique was proposed for fast behavioral simulation [5] .  ... 
doi:10.1145/1065579.1065668 dblp:conf/dac/KimK05a fatcat:tfef7oqdzjavtevrd7ouu3nlnm

SPRINT: A Tool to Generate Concurrent Transaction-Level Models from Sequential Code

Johan Cockx, Kristof Denolf, Bart Vanhoof, Richard Stahl
2007 EURASIP Journal on Advances in Signal Processing  
Generation plus evaluation of an alternative was possible in less than six minutes. This is fast enough to allow extensive exploration of the design space.  ...  A high-level concurrent model such as a SystemC transaction-level model can provide early feedback during the exploration of implementation alternatives for state-of-the-art signal processing applications  ...  ACKNOWLEDGMENT The authors would like to thank Henk Corporaal for the insightful discussions and his valued contribution to this paper.  ... 
doi:10.1155/2007/75373 fatcat:trl4t3i4vrhgravxple4zln424

A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations

Luis Angel D. Bathen, Yongjin Ahn, Sudeep Pasricha, Nikil D. Dutt
2009 2009 10th International Workshop on Microprocessor Test and Verification  
Our exploration engine relies on SystemC-based power/performance models to quickly and accurately evaluate the dynamic power due to memory accesses as well as the expected CPU power consumption.  ...  Power is one of the major constraints considered during the design of embedded software.  ...  This research project was funded in part by the Federal Cyber Service: Scholarship for Service (SFS) Program from the University of California, Irvine.  ... 
doi:10.1109/mtv.2009.19 dblp:conf/mtv/BathenADP09 fatcat:ewdnylnh35eglbxkqjuazlbnue

DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing

Venkatraman Govindaraju, Chen-Han Ho, Tony Nowatzki, Jatin Chhugani, Nadathur Satish, Karthikeyan Sankaralingam, Changkyu Kim
2012 IEEE Micro  
Specialization is a promising direction for improving processor energy efficiency. With functionality specialization, hardware is designed for application-specific units of computation.  ...  The hardware for these specialization approaches have similarities including many functional units and the elimination of perinstruction overheads.  ...  Evaluation Methodology For our performance and energy evaluation, we use a simulation-based approach. We consider a dual-issue OOO processor as our baseline.  ... 
doi:10.1109/mm.2012.51 fatcat:vhuwzkylqzh7bhwyecd7k2bree

Register integration

Amir Roth, Gurindar S. Sohi
2000 Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33  
Our preliminary evaluation shows that a minimal integration configuration can provide performance improvements of up to 8% when applied to current-generation micro-architectures and up to 11.5% when applied  ...  As the processor re-traces portions of the squashed path, integration logic examines each instruction as it is being renamed.  ...  Acknowledgements This work was supported in part by National Science Foundation grants MIP-9505853 and CCR-9900584, donations from Intel Corp. and Sun Microsystems, the University of Wisconsin Graduate  ... 
doi:10.1145/360128.360151 fatcat:bfhabc7h6jg6zk2nh434yfdpnq

Functional abstraction driven design space exploration of heterogeneous programmable architectures

Prabhat Mishra, Nikil Dutt, Alex Nicolau
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Our DSE results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for speci cation and exploration by  ...  Rapid Design Space Exploration (DSE) of a programmable architecture is feasible using an automatic toolkit (compiler, simulator, assembler) generation methodology driven by a n Architecture Description  ...  The approach of 8] uses LISA and SystemC based framework for fast hardware-software co-simulation.  ... 
doi:10.1145/500058.500061 fatcat:oxcvncw66zfjhgdyvqdzsb7cgm

Functional abstraction driven design space exploration of heterogeneous programmable architectures

Prabhat Mishra, Nikil Dutt, Alex Nicolau
2001 Proceedings of the 14th international symposium on Systems synthesis - ISSS '01  
Our DSE results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for speci cation and exploration by  ...  Rapid Design Space Exploration (DSE) of a programmable architecture is feasible using an automatic toolkit (compiler, simulator, assembler) generation methodology driven by a n Architecture Description  ...  The approach of 8] uses LISA and SystemC based framework for fast hardware-software co-simulation.  ... 
doi:10.1145/500001.500061 fatcat:knwr676rgjbkzgvcox3rtt4yhe

Facile

Eric C. Schnarr, Mark D. Hill, James R. Larus
2001 Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation - PLDI '01  
Previously, we developed a technique called fast-forwarding, which applied partial evaluation and memoization to improve the performance of detailed architectural simulations by as much as an order of  ...  While writing a detailed processor simulator is difficult, implementing fast-forwarding is even more complex.  ...  ACKNOWLEDGMENTS Many thanks to Ras Bodik, Charles Consel, Manuvir Das, Jakob Rehof, and Anne Rogers for their helpful comments.  ... 
doi:10.1145/378795.378864 dblp:conf/pldi/SchnarrHL01 fatcat:oculx5covzdktd7qr5r2pwxluy

Facile

Eric C. Schnarr, Mark D. Hill, James R. Larus
2001 SIGPLAN notices  
Previously, we developed a technique called fast-forwarding, which applied partial evaluation and memoization to improve the performance of detailed architectural simulations by as much as an order of  ...  While writing a detailed processor simulator is difficult, implementing fast-forwarding is even more complex.  ...  ACKNOWLEDGMENTS Many thanks to Ras Bodik, Charles Consel, Manuvir Das, Jakob Rehof, and Anne Rogers for their helpful comments.  ... 
doi:10.1145/381694.378864 fatcat:ayrl4c3d4vbdvatkrt2nzzzqla

Chip-Size Evaluation of a Multithreaded Processor Enhanced with a PID Controller [chapter]

Michael Bauer, Mathias Pacher, Uwe Brinkschulte
2010 Lecture Notes in Computer Science  
The overhead introduced by the PID controller implementation in the VHDL model of an embedded Java real-time-system is examined.  ...  In this paper the additional chip size of a Proportional/Integral/Differential (PID) controller in a multithreaded processor is evaluated.  ...  Therefore the parameters determined by the simulator were used to build and configure a VHDL model of the controller.  ... 
doi:10.1007/978-3-642-16256-5_3 fatcat:yvcomouhibat5gdyxfitelchoi

A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors [chapter]

Kai Zhang, ShuMing Chen, Wei Liu, Xi Ning
2013 Lecture Notes in Computer Science  
This paper proposes a fine-grained pipelined implementation of LU decomposition on SIMD processors.  ...  Experimental results show that the proposed technology can achieve a speedup of 1.04x to 1.82x over the native algorithm and can achieve about 89% of the peak performance on the SIMD processor.  ...  This work is supported by the National Natural Science Foundation of China (No.61070036) and HPC Foundation of NUDT.  ... 
doi:10.1007/978-3-642-40820-5_4 fatcat:ysyroxx5abgixozjkpj5s7wyam

Fast and Portable Vector DSP Simulation Through Automatic Vectorization

Jumana Mundichipparakkal, Mohamed A. Bamakhrama, Roel Jordans
2018 Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems - SCOPES '18  
ACKNOWLEDGMENTS The authors would like to thank Saito Hideki from Intel's ICC team for his valuable advice and support.  ...  In class (i), the simulator mimics the execution of the processor by performing all the stages that a processor does, i.e., fetch, decode, and execute during the simulation runtime.  ...  Typically, these executable models embed processor simulators that simulate the different processors integrated in the system.  ... 
doi:10.1145/3207719.3207720 dblp:conf/scopes/Mundichipparakkal18 fatcat:7bilziy2jnfepd5dvplxlsgkjy

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach

Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho
2010 Software, Practice & Experience  
We configure Ruby to model a single-core processor for the experiment.  ...  In Section 4 we describe the concept of TPTS as a framework on which very fast multicore processor simulators can be built.  ...  ACKNOWLEDGEMENTS This work was supported in part by the A. Richard Newton Graduate Scholarship from the ACM Design Automation Conference (DAC) 2008.  ... 
doi:10.1002/spe.956 fatcat:wru5xjqkyjfuhcyfalfquw4vem

System synthesis for multiprocessor embedded applications

Luigi Carro, Márcio Kreutz, Flávio R. Wagner, Márcio Oyamada
2000 Proceedings of the conference on Design, automation and test in Europe - DATE '00  
This paper presents the system synthesis techniques available in S 3 E 2 S, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that can be modeled as a combination  ...  The environment selects processors that best match the desired application by analyzing and comparing processor and application characteristics.  ...  Section 3 presents a very brief overview of the modeling and co-simulation capabilities of S 3 E 2 S, followed in Section 4 by the methodology for the processor selection and the hardware synthesis techniques  ... 
doi:10.1145/343647.343897 fatcat:ewzxvjnzx5ae7gi3d3lpbl6rku
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