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Performance of C++ bit-vector implementations

Vreda Pieterse, Derrick G. Kourie, Loek Cleophas, Bruce W. Watson
<span title="">2010</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cukvzq2vrff3leucluzfpjucqe" style="color: black;">Proceedings of the 2010 Annual Research Conference of the South African Institute of Computer Scientists and Information Technologists on - SAICSIT &#39;10</a> </i> &nbsp;
This paper describes an experimental study to compare the performance of various dynamically resizable bit-vector implementations for the C++ programming language.  ...  Although the results reported in this article is specific to the mentioned C++ libraries, the techniques used to measure and compare the performance of the different libraries go beyond C++ bit-vectors  ...  For C++, there is a number of different bit-vector implementations available to choose from.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1899503.1899530">doi:10.1145/1899503.1899530</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/saicsit/PieterseKCW10.html">dblp:conf/saicsit/PieterseKCW10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mf7dp7abl5gllhiluk6em5xk7a">fatcat:mf7dp7abl5gllhiluk6em5xk7a</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200710060345/https://cs.up.ac.za/cs/vpieterse/pub/PieterseEtAl_SAICSIT2010.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/9b/45/9b45db98aebce5f4db1513843d8de638775f3489.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/1899503.1899530"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Stable Vector Operation implementations, using Intels SIMD Architecture

<span title="2018-01-20">2018</span> <i title="Obuda University"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uwcqb6ghifgnlk73meee4juzsy" style="color: black;">Acta Polytechnica Hungarica</a> </i> &nbsp;
However, these methods usually decrease the performance of computations. In this paper, the most frequently occurring vector-vector addition and dot-product operations are investigated.  ...  Finally, we show the performance of these techniques.  ...  comparison of our stable add implementations and the method of Orchard-Hays, with AVX, using relative tolerance, for two vectors Figure 23 23 Performances of the dot product implementations Performances  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.12700/aph.15.1.2018.1.3">doi:10.12700/aph.15.1.2018.1.3</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mhlpg77urfcenhtkr3bphr35cy">fatcat:mhlpg77urfcenhtkr3bphr35cy</a> </span>
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Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52 [article]

Fabian Boemer, Sejun Kim, Gelila Seifu, Fillipe D. M. de Souza, Vinodh Gopal
<span title="2021-07-09">2021</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Intel HEXL takes advantage of the recent Intel Advanced Vector Extensions 512 (Intel AVX512) instruction set to provide state-of-the-art implementations of the NTT and modular multiplication.  ...  Here, we introduce Intel Homomorphic Encryption Acceleration Library (Intel HEXL), a C++ library which provides optimized implementations of polynomial arithmetic for Intel processors.  ...  ACKNOWLEDGEMENTS We would like to thank Ilya Albrekht for guidance on the AVX512 implementation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2103.16400v3">arXiv:2103.16400v3</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sfnjonx7orhgrgvo7gbrn2h6za">fatcat:sfnjonx7orhgrgvo7gbrn2h6za</a> </span>
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A SIMD algorithm for the detection of epistatic interactions of any order [article]

Christian Ponte-Fernández
<span title="2022-01-07">2022</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Results using the GCC and the Intel compiler show that the 512-bit explicit vector implementation proposed here performs the best out of all of the other implementations evaluated.  ...  The proposed 512-bit vectorization accelerates the original implementation of the algorithm by an average factor of 7 and 12, for GCC and the Intel Compiler, respectively, in the scenarios tested.  ...  this work; and Marcos Horro, for listening to many rants during the development and performance tuning of the AVX vector codes.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2201.02460v1">arXiv:2201.02460v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/quzkhmq5wjaorky3asd6tm6km4">fatcat:quzkhmq5wjaorky3asd6tm6km4</a> </span>
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Efficient Privacy-Preserving Fingerprint-Based Authentication System Using Fully Homomorphic Encryption

Taeyun Kim, Yongwoo Oh, Hyoungshick Kim
<span title="2020-02-13">2020</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sdme5pnua5auzcsjgqmqefb66m" style="color: black;">Security and Communication Networks</a> </i> &nbsp;
The proposed system can perform the fingerprint matching process within about 166 seconds (±0.564 seconds) on average.  ...  One of the most serious concerns is the lack of technology for securely storing fingerprint data used for authentication.  ...  simple logic equations S � X⊕Y⊕C in and C out � MUX X⊕Y (C in , X · Y) that can be performed on bits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2020/4195852">doi:10.1155/2020/4195852</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/7a54ead3rzezvad5s4uw76dd3e">fatcat:7a54ead3rzezvad5s4uw76dd3e</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200215002820/http://downloads.hindawi.com/journals/scn/2020/4195852.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/5c/a0/5ca0e8f53460429c18bc6532eecaeabfc46c665c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2020/4195852"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> hindawi.com </button> </a>

A hybrid implementation of Hamming weight

Enric Morancho
<span title="">2014</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/f3hr4iv3tvhrldoukhnurnloh4" style="color: black;">2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing</a> </i> &nbsp;
Typical bitstring lengths range from the processor's word length to several thousands of bits. A plethora of hamming weight algorithms have been proposed.  ...  On a Sandy Bridge platform, our hybrid implementation outperforms by up to 1.23X and 1.6X the, to the best of our knowledge, best scalar and vector implementations respectively.  ...  ACKNOWLEDGMENT We thankfully acknowledge the support of the Spanish Ministry of Education (TIN2012-34557) and the European Commission in the context of the HiPEAC3 Network of Excellence (FP7/ICT 287759  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/pdp.2014.26">doi:10.1109/pdp.2014.26</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/pdp/Llena14.html">dblp:conf/pdp/Llena14</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/aqpmb7kszzfdbaca2ovobffe3m">fatcat:aqpmb7kszzfdbaca2ovobffe3m</a> </span>
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Montgomery Multiplication Using Vector Instructions [chapter]

Joppe W. Bos, Peter L. Montgomery, Daniel Shumow, Gregory M. Zaverucha
<span title="">2014</span> <i title="Springer Berlin Heidelberg"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/2w3awgokqne6te4nvlofavy5a4" style="color: black;">Lecture Notes in Computer Science</a> </i> &nbsp;
When instantiating modular exponentiation with this parallel version of Montgomery multiplication we observed a performance increase of more than a factor of 1.5 compared to the sequential implementation  ...  This approach is particularly suitable to be computed on 2-way single instruction, multiple data platforms as can be found on most modern computer architectures in the form of vector instruction set extensions  ...  The authors would like to thank: Adam Glass for discussions on ARM SoCs; Patrick Longa for comments on baseline implementations and general help; Jason Mackay for catching mistakes in early drafts; Paul  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-662-43414-7_24">doi:10.1007/978-3-662-43414-7_24</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xl677jumtvejtg6x2mldra7lrm">fatcat:xl677jumtvejtg6x2mldra7lrm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180727205004/https://link.springer.com/content/pdf/10.1007%2F978-3-662-43414-7_24.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ab/e6/abe680e024736e4303b2ea5d5d7f86a247cb0481.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/978-3-662-43414-7_24"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

Autotuning a Random Walk Boolean Satisfiability Solver

Tao Cui, Franz Franchetti
<span title="">2011</span> <i title="Elsevier BV"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cx3f4s3qmfe6bg4qvuy2cxezyu" style="color: black;">Procedia Computer Science</a> </i> &nbsp;
We start from a very compact, reasonable C++ implementation using the STL vector class, and arrive at a fully optimized, parallelized, vectorized C implementation in which we use algorithm-level optimization  ...  The baseline C++ STL implementation requires between 7 and 50 cycles per useful logical operation for the synthetic benchmark; this translates into about 1,700-12,000x performance gain.  ...  However, using the convenience of the STL comes at a performance penalty. ANSI C implementation. In Figure 1 (right) we show a C base-line implementation of the random walk SAT solver.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1016/j.procs.2011.04.238">doi:10.1016/j.procs.2011.04.238</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6mkxrt6u3nhxfjb5t3i5kxskrq">fatcat:6mkxrt6u3nhxfjb5t3i5kxskrq</a> </span>
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Quicker ADC : Unlocking the hidden potential of Product Quantization with SIMD [article]

Fabien André, Anne-Marie Kermarrec, Nicolas Le Scouarnec
<span title="2018-12-21">2018</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
Yet, implementations of nearest neighbor search with Product Quantization have their performance limited by the many memory accesses they perform.  ...  In doing so, Quicker ADC faces the challenge of using efficiently 5,6 and 7-bit shuffles that do not align to computer bytes or words.  ...  Vectors c i are called centroids, and the set of centroids C, of cardinality k, is the codebook.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1812.09162v1">arXiv:1812.09162v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4gupzrkwgndgxof3malq4tkh2u">fatcat:4gupzrkwgndgxof3malq4tkh2u</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20191022215417/https://arxiv.org/pdf/1812.09162v1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/64/f8/64f8f8508ceefc2c29b1c0b77b699dbc904eb24e.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/1812.09162v1" title="arxiv.org access"> <button class="ui compact blue labeled icon button serp-button"> <i class="file alternate outline icon"></i> arxiv.org </button> </a>

Efficient Parallel Implementation of Matrix Multiplication for Lattice-Based Cryptography on Modern ARM Processor

Taehwan Park, Hwajeong Seo, Junsub Kim, Haeryong Park, Howon Kim
<span title="2018-09-24">2018</span> <i title="Hindawi Limited"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/sdme5pnua5auzcsjgqmqefb66m" style="color: black;">Security and Communication Networks</a> </i> &nbsp;
CCA key generation step enhances the performance by 7.04%, 3.66%, 7.57%, and 9.32% over previous state-of-the-art implementations.  ...  In this paper, we propose an efficient parallel implementation of matrix multiplication and vector addition with matrix transpose using ARM NEON instructions on ARM Cortex-A platforms.  ...  In their paper, they proposed AVX2 implementation and performance of CRYSTALS-Kyber.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1155/2018/7012056">doi:10.1155/2018/7012056</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/a5aapx5yvjh5tl6f6vrnrn4iem">fatcat:a5aapx5yvjh5tl6f6vrnrn4iem</a> </span>
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Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution

Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel
<span title="2022-04-30">2022</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/c2ubcasn2jaunmzahfcdaeyvry" style="color: black;">ACM Journal on Emerging Technologies in Computing Systems</a> </i> &nbsp;
Operations are performed on large vectors of data occupying the entire physical row of C-SRAM array, leading to high performance gains.  ...  We introduce the C-SRAM solution in this article as an integrated vector processing unit to be used by a scalar processor as an energy-efficient and high performing co-processor.  ...  We evaluate also the impact of different C-SRAM size on the performance and energy gains. C-SRAM Implementation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3485823">doi:10.1145/3485823</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/56ajw5q2snehvd6h5g7wluckry">fatcat:56ajw5q2snehvd6h5g7wluckry</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20220616013137/https://dl.acm.org/doi/pdf/10.1145/3485823" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/49/ce/49cec3b09cba336c28292adbe4068f229b2e53d7.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3485823"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> acm.org </button> </a>

Enhancing the Matrix Transpose Operation Using Intel Avx Instruction Set Extension

Ahmed Sherif Zekri
<span title="2014-06-30">2014</span> <i title="Academy and Industry Research Collaboration Center (AIRCC)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/plyx54ayrbefvje4gawexbdyty" style="color: black;">International Journal of Computer Science &amp; Information Technology (IJCSIT)</a> </i> &nbsp;
In this paper, we consider the acceleration of the matrix transpose operation using the 256-bit Intel advanced vector extension (AVX) instructions.  ...  Therefore, accelerating these kernel operations on microprocessors, which are the building blocks or large high-performance computing systems, will definitely boost the performance of the aforementioned  ...  Therefore, our implementation may fill a gap when transforming old 128-bit SSE implementations of matrix and vector computations into newer 256-bit AVX implementations and even future extensions to 512  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5121/ijcsit.2014.6305">doi:10.5121/ijcsit.2014.6305</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/sonpx6rezfcondu33otynktipu">fatcat:sonpx6rezfcondu33otynktipu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180603063130/http://www.airccse.org/journal/jcsit/6314ijcsit05.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e2/4c/e24c4b4e3ed1d72dc33f6503a877338daadd9ca7.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5121/ijcsit.2014.6305"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> Publisher / doi.org </button> </a>

HACL*

Jean-Karim Zinzindohoué, Karthikeyan Bhargavan, Jonathan Protzenko, Benjamin Beurdouche
<span title="">2017</span> <i title="ACM Press"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rau5643b7ncwvh74y6p64hntle" style="color: black;">Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security - CCS &#39;17</a> </i> &nbsp;
We show how to verify code that relies on low-level hardware features like 128-bit integers and vector instructions.  ...  When compiled with GCC on 64-bit platforms, our implementations are as fast as the fastest C implementations in OpenSSL and libsodium, significantly faster than the reference C code in TweetNaCl and SuperCop  ...  to perform on 128, 256, and now 512-bit registers, treated as vectors of 8, 16, 32, or 64-bit integers.  ... 
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Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography

Davide Zoni, Andrea Galimberti, William Fornaciari
<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
C sp = 2 3 (9) To this end, the vector-matrix multiplication between b and C sp can be computed as the sum of the dense vector shiftrotated to the left by amounts equal to the elements of C sp .  ...  For example, Equation 8 shows the vector-matrix multiplication between a 4-bit row-vector (b) and a 4 × 4, binary, circulant matrix (C).  ...  ., the feasible one providing the best performance in terms of the time to compute the entire decoding.  ... 
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<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200902152652/https://ieeexplore.ieee.org/ielx7/6287639/6514899/09180360.pdf?tp=&amp;arnumber=9180360&amp;isnumber=6514899&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e9/97/e997998562dd4e849332d747386859b7fc5a0382.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2020.3020262"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>

Neural Network Implementation Using Fpga: Issues And Application

A. Muthuramalingam, S. Himavathi, E. Srinivasan
<span title="2008-12-22">2008</span> <i title="Zenodo"> Zenodo </i> &nbsp;
Using the proposed method of implementation a neural network based application, namely, a Space vector modulator for a vector-controlled drive is presented  ...  .Hardware realization of a Neural Network (NN), to a large extent depends on the efficient implementation of a single neuron.  ...  ACKNOWLEDGMENT The research is supported by the grants from the All India Council for Technical Education (AICTE), a statutory body of Government of India. File Number: 8020/RID/TAPTEC-32/2001-02.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.1084402">doi:10.5281/zenodo.1084402</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/jcp4wdpyajdwfj3u2kvo47tio4">fatcat:jcp4wdpyajdwfj3u2kvo47tio4</a> </span>
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