Filters








15,106 Hits in 6.4 sec

Performance and power optimization through data compression in Network-on-Chip architectures

Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das
2008 High-Performance Computer Architecture  
Even in the case of NC -where the data is compressed only when passing through the NoC fabric of the NUCA architecture and stored uncompressed -performance and power savings of up to 32% and 21%, respectively  ...  These benefits are orthogonal to any router architecture and make a strong case for utilizing compression for optimizing the performance and power envelope of NoC architectures.  ...  Hence, data compression in larger multi-core systems is expected to provide similar performance and power optimization.  ... 
doi:10.1109/hpca.2008.4658641 dblp:conf/hpca/DasMNPNIYD08 fatcat:su5ocscq6bhajeqrlqjueltxmm

A novel 3D NoC scheme for high throughput unicast and multicast routing protocols

2016 Tehnički Vjesnik  
The proposed design shows remarkable results in terms of power efficiency and network throughput.  ...  In this scheme, proposed for 3D-NoC, the data to be transmitted is compressed on the transmitting side, so that the data packet is reduced before transmitting.  ...  On the other hand, Network on Chip (NoC) is emerging as a promising technology [3] to overcome the restricted access of bus architecture in System on Chip (SoC).  ... 
doi:10.17559/tv-20141230061413 fatcat:jxa5oy5gtjd5lgp6gi3lw6ymna

Frequent value compression in packet-based NoC architectures

Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang, Li Zhao
2009 2009 Asia and South Pacific Design Automation Conference  
In this paper, we propose a novel scheme that exploits Frequent Value compression to optimize the power and performance of NoC.  ...  For scalability reasons, a large on-chip cache is often divided into smaller banks that are interconnected through packet-based Network-on-Chip (NoC).  ...  Recent studies showed that it is increasingly important to optimize on-chip interconnection network under chip area and power constraints [7] .  ... 
doi:10.1109/aspdac.2009.4796434 dblp:conf/aspdac/ZhouZDXZYZ09 fatcat:ehltpoipzzgqjb5sibwwgbiaji

Author Index

2020 2020 IEEE 33rd International System-on-Chip Conference (SOCC)  
Architecture for the Reduction in VDF Based on a Class Group Sonoda, Shoya FR5.3 236 Dynamic Supply and Threshold Voltage Scaling Towards Runtime Energy Optimization over a Wide Operating Performance  ...  Learning FDT.2 258 Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC Gu, Shouzhen WS1.2 31 Architectural Exploration on Racetrack Memories  ... 
doi:10.1109/socc49529.2020.9524726 fatcat:qluzc5nlwbbyrf7iy5d4pnsrhy

Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs

Antonio Flores, Manuel E. Acacio, Juan L. Aragón
2010 Journal of systems architecture  
High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip.  ...  As the number of cores inside a Chip MultiProcessor (CMP) increases, the interconnection network will have significant impact on both overall performance and energy consumption as previous studies have  ...  Acknowledgments This work has been jointly supported by the Spanish MEC and European Commission FEDER funds under grants ''Consolider Ingenio-2010 CSD2006-00046" and ''TIN2006-15516-C4-03", and also by  ... 
doi:10.1016/j.sysarc.2010.05.006 fatcat:rf35lf4tcjhbfcimkcdwywwqj4

On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing

Denny Lie, Kwanyeob Chae, Saibal Mukhopadhyay
2013 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)  
the power dissipation, and maintain a target image rate under varying channel condition.  ...  This paper explores the design space of the multi-segment architecture for the wavelet based image compression, including the number of segments, the operating frequency, and the supply voltage to reduce  ...  Acknowledgement: This work is supported in part by National Science Foundation CAREER Award (#1054429).  ... 
doi:10.1109/nanoarch.2013.6623057 dblp:conf/nanoarch/LieCM13 fatcat:bwhdbmrk5je7nofchu6krjmoae

Energy-Efficient System-Level Design [chapter]

Luca Benini, Giovanni De Micheli
2002 Power Aware Design Methodologies  
and communication channel as well as system and application software onto a single chip.  ...  The complexity of current and future integrated systems requires a paradigm shift towards component-based design techno logies that enable the integration of large computational cores, memory hierarchies  ...  One may be led to conclude that a low-latency memory architecture will also be a low -power architecture and that memory performance optimization implies power optimization.  ... 
doi:10.1007/0-306-48139-1_16 fatcat:rikxlmoqmjfd3o3whfmbnvymwm

Application-driven energy-efficient architecture explorations for big data

Xiaoyan Gu, Rui Hou, Ke Zhang, Lixin Zhang, Weiping Wang
2011 Proceedings of the 1st Workshop on Architectures and Systems for Big Data - ASBD '11  
In addition, we propose a mechanism that enables the accelerators to perform more efficient data compression/decompression.  ...  Based on our findings, we demonstrate the necessity of using a heterogeneous architecture for energy-efficient big data processing.  ...  Figure 6 : 6 Off-chip and on-chip accelerator implementations 5.1 Heterogeneous architecture: Low-power cores with hardware accelerators Figure 7 : 7 Multiple interleaved compression or decompression  ... 
doi:10.1145/2377978.2377984 fatcat:meyprx3dgjdyveetfu4a26jfj4

2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38

2019 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Zorian, Y.  ...  ., +, TCAD Feb. 2019 199-207 Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.  ...  ., +, TCAD Oct. 2019 1914-1927 Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.  ... 
doi:10.1109/tcad.2020.2964359 fatcat:qjr6i73tkrgnrkkmtjexbxberm

Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework [article]

Muhammad Shafique, Alberto Marchisio, Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif
2021 arXiv   pre-print
Afterward, we discuss how to further improve the performance (latency) and the energy efficiency of Edge AI systems through HW/SW-level optimizations, such as pruning, quantization, and approximation.  ...  Deploying advanced Neural Networks (NN), such as deep neural networks (DNNs) and spiking neural networks (SNNs), that offer state-of-the-art results on resource-constrained edge devices is challenging  ...  ACKNOWLEDGMENTS This work was partly supported by Intel Corporation through Gift funding for the project "Cost-Effective Dependability for Deep Neural Networks and Spiking Neural Networks".  ... 
arXiv:2109.09829v1 fatcat:rfbshpbaevgxdi4mnjskis5lty

Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs

Antonio Flores, Manuel E. Acacio, Juan L. Aragón
2008 2008 37th International Conference on Parallel Processing  
Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption.  ...  In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs that combines both address compression with a heterogeneous interconnect.  ...  Acknowledgments This work has been jointly supported by the Spanish MEC and European Commission FEDER funds under grants "Consolider Ingenio-2010 CSD2006-00046" and "TIN2006-15516-C4-03".  ... 
doi:10.1109/icpp.2008.33 dblp:conf/icpp/FloresAA08 fatcat:icsnub6qoba2fapgvr2lbe425a

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs [article]

Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stephane Emery, Luca Benini
2021 arXiv   pre-print
This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance.  ...  Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved.  ...  and optimization Neural network can generally be described using nested loops, with the outer most one looping through the layers of the network.  ... 
arXiv:2106.12810v1 fatcat:gx7cspazc5fdfoi64t2zjth7am

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., and Gielen, G. G. E., Globally Reliable Variation-Aware Sizing Ko, H.  ...  ., +, TCAD Sept. 2009 1321-1333 DC-DC power converters Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips.  ...  Hu, S., +, TCAD June 2009 818-825 Optimal Design of the Power-Delivery Network for Multiple Voltage-Island System-on-Chips.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku

ASIC Implementation of Neural Network Based Image Compression

K.Venkata Ramanaiah, Cyril Prasanna Raj
2011 Journal of clean energy technologies  
In this paper the main focus is development of new architectures for neural network based image compression optimizing area, power and speed as specific to ASIC implementation, and comparison with FPGA  ...  Image data consumes enormous bandwidth and storage space. Neural networks can be used for image compression.  ...  The basic architecture for image compression using neural network is shown in figure1. II.  ... 
doi:10.7763/ijcte.2011.v3.356 fatcat:dkanrsys3bdv3ddj2guk3oethe

PERFORMANCE ANALYSIS AND IMPLEMENTATION OF MODIFIED SDM BASED NOC FOR MPSOC ON SPARTAN6 FPGA

Y. Amar Babu .
2016 International Journal of Research in Engineering and Technology  
network-On-chip.  ...  This paper presents modified spatial division multiplexing based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient SDM based NoC.This  ...  Our report concludes that area is optimized at network interface level and router side which can be compared with any other network-on-chip architectures for area optimization V.  ... 
doi:10.15623/ijret.2016.0502062 fatcat:pymil34o5rhjrgpt2rn2zb4zly
« Previous Showing results 1 — 15 out of 15,106 results