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Multi-core design automation challenges

John A Darringer
2007 Proceedings - Design Automation Conference  
This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and  ...  The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions.  ...  INTEGRATED EARLY ANALYSIS Early in the design of a processor, a small team of experts in performance analysis, power estimation, chip layout, packaging, bus architectures and memory hierarchies are brought  ... 
doi:10.1145/1278480.1278670 dblp:conf/dac/Darringer07 fatcat:mwkjduewn5gcnicdamz57er3tu

Multi-Core Design Automation Challenges

John A Darringer
2007 Proceedings - Design Automation Conference  
This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and  ...  The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions.  ...  INTEGRATED EARLY ANALYSIS Early in the design of a processor, a small team of experts in performance analysis, power estimation, chip layout, packaging, bus architectures and memory hierarchies are brought  ... 
doi:10.1109/dac.2007.375266 fatcat:jycsxptkunbfheu4pgo4zx32vm

Method for teaching parallelism on heterogeneous many-core processors using research projects

Henrique Cota de Freitas
2013 2013 IEEE Frontiers in Education Conference (FIE)  
The proposed method focuses on projects convergence to teach how to extract characteristics from benchmark traces in order to simulate many-core processors based on Networks-on-Chip.  ...  For instance, one processor chip can be built with 1,000 processing cores. Moreover, this type of processor is designed to achieve scalability and performance based on heterogeneous cores.  ...  Thanks to all students of CArT.  ... 
doi:10.1109/fie.2013.6684797 dblp:conf/fie/Freitas13 fatcat:ohdvrddodrfhnmurdhlxkl2n5i

Optimizing Data-Center TCO with Scale-Out Processors

Boris Grot, Damien Hardy, Pejman Lotfi-Kamran, Babak Falsafi, Chrysostomos Nicopoulos, Yiannakis Sazeides
2012 IEEE Micro  
Scale-out workloads prevalent in largescale data centers rely on in-memory  ...  We are in the midst of an information revolution, driven by ubiquitous access to vast data stores via a variety of richly networked platforms.  ...  We thank the EuroCloud project partners for inspiring the Scale-Out Processors.  ... 
doi:10.1109/mm.2012.71 fatcat:gumdjqh3mvap3jugapi3m3uucq

Ethernet Packet Processor for SoC Application [article]

Raja Jitendra Nayaka, R. C. Biradar
2012 arXiv   pre-print
This paper describes the design of ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification  ...  The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications.  ...  The increase in the number of cores that can be integrated on a single chip has forced the designer to use computer network concepts for design of System on Chip (SoC).  ... 
arXiv:1207.5138v1 fatcat:oqkyf3ewz5ailjvwxm5g2puyna

Understanding the Impact of the Interconnection Network Performance of Multi-core Cluster Architectures

Norhazlina Hamid, Robert Walters, Gary Wills
2016 Journal of Computers  
The communication between two processor cores on the same chip is the intra-chip network (AC).  ...  Messages will be divided into a number of cores by the AC network, which acts as a connector between two or more processor cores on the same chip.  ...  Acknowledgment The authors acknowledge the award of a Malaysia Fellowship Training scholarship (HLP), Public Service Department of Malaysia, to Norhazlina Hamid to allow this research to be undertaken.  ... 
doi:10.17706/jcp.11.2.132-139 fatcat:ldvs5gdcobdj7meooqphmznwfy

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator

Eduardo André Neves
2018 Journal of Computers  
The Rocket Chip Generator is one of these tools.  ...  This article presents the analysis and comparison of two powerful tools to explore design space and study multi-core microprocessors.  ...  Network-on-Chip In order to allow scalability, Heracles uses a Network on Chip (NoC) architecture for its data communication infrastructure.  ... 
doi:10.17706/jcp.13.5.555-563 fatcat:i4km2rnotfcpbgd7eqci6o6d6a

An efficient task mapping algorithm with power-aware optimization for network on chip

Wei Hu, Qingsong Shi, Yonghao Wang, Kai Zhang, Jun Liu, Xiaoming Liu, Hong Guo
2016 Journal of systems architecture  
The cores are connected by lines and organized as a network, which is called network on chip (NOC) as the promising paradigm of the processor design.  ...  The processor cores on NOC are distributed on the chip via the lines not the traditional buses [6] [7] . The on-chip network makes NOC more scalable in communication.  ...  Acknowledgements This work was supported by National Natural Science Foundation of China (Granted No. 61100055 and 31201121).  ... 
doi:10.1016/j.sysarc.2016.04.006 fatcat:3wlx3prrmvd53at7w475y7okdu

Sunway supercomputer architecture towards exascale computing: analysis and practice

Jiangang Gao, Fang Zheng, Fengbin Qi, Yajun Ding, Hongliang Li, Hongsheng Lu, Wangquan He, Hongmei Wei, Lifeng Jin, Xin Liu, Daoyong Gong, Fei Wang (+5 others)
2021 Science China Information Sciences  
Moreover, this paper proposes the Sunway computer architecture towards exascale computing in which the many-core processor, network chipset and software system are all domestically-designed.  ...  In recent years, the improvements of system performance and energy efficiency for supercomputers have faced increasing challenges, which create more intensive demands on the architecture design for realizing  ...  Figure 9 ( 9 Color online) The on-chip hierarchical memory architecture of SW many-core processors.  ... 
doi:10.1007/s11432-020-3104-7 fatcat:ocmhnpa2dng2lhqhldgbcdfw2a

Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)

Haroon-Ur-Rashid Khan, Feng Shi, WeiXing Ji, YuJin Gao, YiZhuo Wang, CaiXia Liu, Ning Deng, JiaXin Li
2010 Chinese Science Bulletin  
We propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network, the "lower layer complete connect".  ...  Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC).  ...  Many interconnection networks for on-chip multiprocessor architecture have been proposed in the literature, over the past three decades.  ... 
doi:10.1007/s11434-010-4118-z fatcat:anzn23bafnchjd2a7n64ynfqce

High Performance Ethernet Packet Processor Core for Next Generation Networks

Raja Jitendra Nayaka
2012 International Journal of Next-Generation Networks  
This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification  ...  Application specific processors require high performance, low power and high degree of programmability is the limitation in many general processor based applications.  ...  SYSTEM ON CHIP (SoC) System on chip (SoC or SOC) refers to integrating many functional or peripherals of a embedded system or other electronic system into a single integrated circuit .  ... 
doi:10.5121/ijngn.2012.4307 fatcat:izmm5kawabgspd62bonia4p2km

HANDS

Davide Zoni, Simone Corbetta, William Fornaciari
2012 Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design - ISLPED '12  
In current multi-core scenario, Networks-on-Chip (NoC) represent a suitable choice to face the increasing communication and performance requirements, however introducing additional design challenges to  ...  We present the Heterogeneous Architectures and Networks-on-Chip Design and Simulation framework for large-scale highperformance computer simulation, integrating performance, power, thermal and reliability  ...  Network-on-Chip (Polaris) [15] design-space exploration Hsieh et al. microarchitecture, power (SST) [6] and thermal Lis et al. many-core processors, (HORNET) [10] mainly NoC interconnect Bartolini  ... 
doi:10.1145/2333660.2333721 dblp:conf/islped/ZoniCF12 fatcat:6amhn54rubfbblq57kalvntio4

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Lei Zhang, Yinhe Han, Qiang Xu, Xiao wei Li, Huawei Li
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different.  ...  Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores.  ...  In addition, with many cores implemented on-chip, we may get various types of degraded chips (with different number of faulty cores) after fabrication and the yield of the demanded -core processor cannot  ... 
doi:10.1109/tvlsi.2008.2002108 fatcat:hlh257nyynek3erogi5bqd2v4m

What GPU Computing Means for High-End Systems

Richard Vuduc, Kent Czechowski
2011 IEEE Micro  
(P is the number of processors, where each processor is multicore or many-core with p cores.)  ...  Since the FFT is heavily I/O bound, the time to perform flops is negligible and can be ignored for even Figure 1 . Illustration of balance principles: a hypothetical multi-/many-core processor (a).  ... 
doi:10.1109/mm.2011.78 fatcat:g5a4gbr3gnaf5j64le3tnfk7lm

Abstract Machine Models and Proxy Architectures for Exascale Computing

J.A. Ang, R.F. Barrett, R.E. Benner, D. Burke, C. Chan, J. Cook, D. Donofrio, S.D. Hammond, K.S. Hemmert, S.M. Kelly, H. Le, V.J. Leung (+6 others)
2014 2014 Hardware-Software Co-Design for High Performance Computing  
The most significant consequence of this assertion is the impact on the scientific applications that run on current high performance computing (HPC) systems, many of which codify years of scientific domain  ...  They allow for application performance analysis and hardware optimization opportunities.  ...  Homogeneous Many-core Processor Model Like a system-area interconnect, the on-chip network may "taper" and vary depending on the core pair and network topology.  ... 
doi:10.1109/co-hpc.2014.4 dblp:conf/sc/AngBBBCCDHHKLLR14 fatcat:sot6sfvdhbcwfbspps77auhwum
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