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Survey on microprocessor architecture and development trends

YaoYingbiao, Zhang Jianwu, Zhao Danying
2008 2008 11th IEEE International Conference on Communication Technology  
To improve the performance of microprocessor, many kinds of novel architecture, such as multi-thread processor, CMP, PIM, and reconfigurable computing processor, have been proposed.  ...  This paper summarizes characteristic of these kinds of architecture, and predicts the development trends of microprocessor in the future.  ...  As a result, the method by increasing the frequency of microprocessors to improve performance of has come to end. III. ADVANCED MICROARCHITECTURES OF PROCESSORS A.  ... 
doi:10.1109/icct.2008.4716247 fatcat:3mrfuvgwcrcyjbcm2an6nuymri

Retrospective: simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
Several other projects had also looked at various forms of multithread, superscalar issue.  ...  However, as we examined them, each of these studies seemed to be limited in some way by the constraints of a particular hardware architecture in which it was embedded.  ...  Dean Tullsen finished his PhD at University of Washington on the topic of Simultaneous Multithreading.  ... 
doi:10.1145/285930.285971 dblp:conf/isca/TullsenEL98 fatcat:jdxfaqaaencwvmsvs6mj4yfubi

A survey of processors with explicit multithreading

Theo Ungerer, Borut Robič, Jurij Šilc
2003 ACM Computing Surveys  
Hardware multithreading is becoming a generally applied technique in the next generation of microprocessors.  ...  Several multithreaded processors are announced by industry or already into production in the areas of high-performance microprocessors, media, and network processors.  ...  INTERLEAVED AND BLOCKED MULTITHREADING IN CURRENT AND PROPOSED MICROPROCESSORS High-Performance Processors Cray MTA.  ... 
doi:10.1145/641865.641867 fatcat:u6x7jdmkfvexnm3culskjsoxwi

Multithreaded Processors

T. Ungerer
2002 Computer journal  
The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors.  ...  Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor  ...  an analytical model of multithreaded superscalar performance, backed up by simulation.  ... 
doi:10.1093/comjnl/45.3.320 fatcat:hlkkabuhrzhkrmuyqomzfmc6zm

Multi-Threaded Processors [chapter]

David Padua, Amol Ghoting, John A. Gunnels, Mark S. Squillante, José Meseguer, James H. Cownie, Duncan Roweth, Sarita V. Adve, Hans J. Boehm, Sally A. McKee, Robert W. Wisniewski, George Karypis (+29 others)
2011 Encyclopedia of Parallel Computing  
The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors.  ...  Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor  ...  an analytical model of multithreaded superscalar performance, backed up by simulation.  ... 
doi:10.1007/978-0-387-09766-4_423 fatcat:heb3n2cfwnbi5nvxv5kvxd2xgm

Modeling technology impact on cluster microprocessor performance

L. Codrescu, S. Nugent, J. Meindl, D.S. Wills
2003 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay.  ...  This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor  ...  ACKNOWLEDGMENT The authors acknowledge the significant research of the members of the GigaScale Integration (GSI) group on which GENESYS is built, and thank the anonymous reviewers and associate editor  ... 
doi:10.1109/tvlsi.2003.817512 fatcat:utzohu2kkzalvl7surnbs63khe

Multithreading decoupled architectures for complexity-effective general purpose computing

Michael Sung, Ronny Krashinsky, Krste Asanović
2001 SIGARCH Computer Architecture News  
A proposal for a multithreaded decoupled control/access/execute architecture is presented as a platform for achieving high performance on general purpose workloads.  ...  It is argued that such a decoupled architecture is more complexity-effective and scalable than comparable superscalar processors, which incorporate enormous amounts of complexity for modest performance  ...  To exploit the advantages out of both superscalar and decoupled architectures, we can consider implementing the control processor in a DCAE design as a more capable high-performance microprocessor.  ... 
doi:10.1145/563647.563658 fatcat:fjmdpove5ravhclvctbfurz6im

A survey of new research directions in microprocessors

J. Šilc, T. Ungerer, B. Robic
2000 Microprocessors and microsystems  
Current microprocessors utilise the instruction-level parallelism by a deep processor pipeline and the superscalar instruction issue technique.  ...  This paper discusses and compares the performance potential of these complex uniprocessors. ᭧  ...  Acknowledgements We thank the referees of this paper for many helpful comments.  ... 
doi:10.1016/s0141-9331(00)00072-7 fatcat:55y6n4wzijaeppl3l5qp6x2koa

Effects of multithreading on cache performance

H. Kwak, B. Lee, A.R. Hurson, Suk-Han Yoon, Woo-Jong Hahn
1999 IEEE transactions on computers  
In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion.  ...  MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling.  ...  In order to evaluate the performance of the MVP and its cache effects, we developed a simulator that integrates a general purpose thread package and a multithreaded superscalar simulator.  ... 
doi:10.1109/12.752659 fatcat:6b24u3lsnrcoflhbfb453n46sa

Exploiting instruction- and data-level parallelism

R. Espasa, M. Valero
1997 IEEE Micro  
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately.  ...  Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications.  ...  This work was supported by the Ministry of Education of Spain under contract TIC 0429/95 and by the CEPBA (European Center for Parallelism of Barcelona).  ... 
doi:10.1109/40.621210 fatcat:5oanmvkc3vfe7lq3w4jcdbkmjy

Study of Various Factors Affecting Performance of Multi-Core Processors

Nitin Chaturvedi, Gurunarayanan S
2013 International Journal of Distributed and Parallel systems  
As Chip Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single chip.  ...  In addition the virtualization of these computation resources exposes the system to a mix of diverse and competing workloads.  ...  It is possible to design a dynamically scheduled superscalar microprocessor using reservation stations, the most recent implementations of dynamic superscalar processors have used a structure similar to  ... 
doi:10.5121/ijdps.2013.4404 fatcat:ipcaejvdybaipejw5ehavdham4

Microarchitecture and Performance Analysis of Godson-2 SMT Processor

Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
2006 Computer Design (ICCD '99), IEEE International Conference on  
This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-of-order execution high  ...  The condition for implementing correct memory consistency model in Godson-2 SMT processor is studied and a new register-level sharing and synchronization scheme is proposed.  ...  As a single chip contains over one billion transistors, the exploitation of thread-level parallelism becomes the trend of high performance microprocessor design.  ... 
doi:10.1109/iccd.2006.4380860 dblp:conf/iccd/LiXHT06 fatcat:vd4hexqb6ja6ji6ukt5cr7tjvi

A single-chip multiprocessor

B.A. Nayfeh, K. Olukotun
1997 Computer  
Relative performance of superscalar, simultaneous multithreading, and chip multiprocessor architectures compared to a baseline, 2-issue superscalar architecture.  ...  As a result, they perform and utilize area comparably on multithreaded code.  ... 
doi:10.1109/2.612253 fatcat:l645n6krxnaphalnk5w6pogwye

Maximizing CMP throughput with mediocre cores

J.D. Davis, J. Laudon, K. Olukotun
2005 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)  
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications.  ...  We examine CMTs with inorder scalar processor cores, 2-way or 4-way in-order superscalar cores, private primary instruction and data caches, and a shared secondary cache.  ...  Acknowledgements We would like to thank Cong Fu, Venkatesh Iyengar, and the entire Niagara Architecture Group for their assistance with the performance modeling.  ... 
doi:10.1109/pact.2005.42 dblp:conf/IEEEpact/DavisLO05 fatcat:h5rgzutzjndzhdtyndkrewxxhm

Simultaneous multithreading

Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
1998 25 years of the international symposia on Computer architecture (selected papers) - ISCA '98  
Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multithreading.  ...  We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor. and single-chip, multiple-issue multiprocessing  ...  Acknowledgments We would like to thank JohnO'Donnell from EquatorTechnologies, Inc. and Tryggve Fossum of Digital Equipment Corporation for access to the source for the Alpha AXP version of the Multiflow  ... 
doi:10.1145/285930.286011 dblp:conf/isca/TullsenEL98a fatcat:wzwmqqcnj5bz3faupjps7d6tay
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