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Performance Improvement via Always-Abort HTM

Joseph Izraelevitz, Lingxiang Xiang, Michael L. Scott
2017 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)  
With always-abort HTM (AAHTM), no such synchronization is necessary, because there is no risk of accidentally committing a transaction that has seen inconsistent state.  ...  This work proposes and discusses the implications of adding a new feature to hardware transactional memory, allowing a program to specify that a transaction should always abort (even if it executes a commit  ...  Furthermore, by using the busywait time to prefetch for the critical section, we can reduce the time threads hold the lock and increase throughput via always-abort HTM (tatas-aahtm).  ... 
doi:10.1109/pact.2017.16 dblp:conf/IEEEpact/IzraelevitzXS17 fatcat:n3f45w4iira4zglhwrh3gzn3ay

Applying HTM to an OLTP System

David Cervini, Danica Porobic, Pınar Tözün, Anastasia Ailamaki
2015 Proceedings of the 11th International Workshop on Data Management on New Hardware - DaMoN'15  
We find that HTM can improve performance of the TATP workload by 13-17% when applied judiciously.  ...  However, attempting to replace all synchronization reduces performance compared to the baseline case due to high percentage of aborts caused by the limitations of the current HTM implementation.  ...  While HTM can improve performance in some cases, the limitations of the current hardware implementation can also cause performance drops in case of frequent aborts.  ... 
doi:10.1145/2771937.2771946 dblp:conf/damon/CerviniPTA15 fatcat:ktn73p5eibh5tbt7zcojvx4jle

Optimistic Concurrency Control for Real-world Go Programs (Extended Version with Appendix) [article]

Zhizhou Zhang, Milind Chabbi, Adam Welc, Timothy Sherwood
2021 arXiv   pre-print
Profitability is driven by both static analyses of critical sections and dynamic analysis via execution profiles.  ...  A custom HTM library, using perceptron, learns concurrency behavior and dynamically decides whether to use HTM in the rewritten lock/unlock points.  ...  Our solution is to always apply the transformations on the candidates found in inner regions, and handle mismatches at runtime via HTM aborts iff executing on the fastpath.  ... 
arXiv:2106.01710v1 fatcat:joiitibajndepjgnxh5u67ykpy

Performance pathologies in hardware transactional memory

Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood
2007 Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07  
ABSTRACT Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution.  ...  We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FRIENDLYFIRE, STARVINGWRITER, SERIALIZEDCOMMIT  ...  . 5 Execution Time Breakdown for Base HTM Systems Figure 6 . 6 Performance Comparision for enhanced HTM systems LL B improves performance by eliminating RESTARTCONVOY.  ... 
doi:10.1145/1250662.1250674 dblp:conf/isca/BobbaMVYHSW07 fatcat:qi5ry4a6ijgmtc7bxqgkjzphi4

Performance pathologies in hardware transactional memory

Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood
2007 SIGARCH Computer Architecture News  
ABSTRACT Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution.  ...  We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FRIENDLYFIRE, STARVINGWRITER, SERIALIZEDCOMMIT  ...  . 5 Execution Time Breakdown for Base HTM Systems Figure 6 . 6 Performance Comparision for enhanced HTM systems LL B improves performance by eliminating RESTARTCONVOY.  ... 
doi:10.1145/1273440.1250674 fatcat:rgvqeseoy5bhteq3eb234g2gai

Performance Pathologies in Hardware Transactional Memory

Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood
2008 IEEE Micro  
ABSTRACT Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution.  ...  We identify seven performance pathologies-interactions between workload and system that degrade performance-as the root cause of many performance differences: FRIENDLYFIRE, STARVINGWRITER, SERIALIZEDCOMMIT  ...  . 5 Execution Time Breakdown for Base HTM Systems Figure 6 . 6 Performance Comparision for enhanced HTM systems LL B improves performance by eliminating RESTARTCONVOY.  ... 
doi:10.1109/mm.2008.11 fatcat:cgiqc6oxmfgwfjb4a62z54qkvu

To lock, swap, or elide

Darko Makreshanski, Justin Levandoski, Ryan Stutsman
2015 Proceedings of the VLDB Endowment  
While lock-freedom entails design complexity and extra mechanism, it has performance advantages in several scenarios, especially high-contention cases where readers proceed uncontested (whereas HTM aborts  ...  We find that using HTM to implement a multi-word compare-and-swap greatly reduces lockfree programming complexity at the cost of only a 10-15% performance degradation.  ...  However, these are not the only reasons for aborts with Intel's current HTM implementation. Avoiding memory page faults. When a transaction encounters a page fault it always aborts.  ... 
doi:10.14778/2809974.2809990 fatcat:io6bn72bpbeppgnwh44onkdnoa

Virtues and limitations of commodity hardware transactional memory

Nuno Diegues, Paolo Romano, Luís Rodrigues
2014 Proceedings of the 23rd international conference on Parallel architectures and compilation - PACT '14  
questions by conducting the largest study on TM to date, comparing different locking techniques, hardware and software TMs, as well as different combinations of these mechanisms, from the dual perspective of performance  ...  Our study sheds a mix of light and shadows on currently available commodity HTM: on one hand, we identify workloads in which HTM clearly outperforms any alternative synchronization mechanism; on the other  ...  In both [21, 20] the authors assess the behaviour of different HTM implementations via simulation (the latter focusing on embedded systems).  ... 
doi:10.1145/2628071.2628080 dblp:conf/IEEEpact/DieguesRR14 fatcat:vatksqehx5fxzoh23ysiz2n4fi

Version management alternatives for hardware transactional memory

Marc Lupon, Grigorios Magklis, Antonio González
2008 Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08  
In this paper, we show that aborts are frequent especially for applications with coarse-grain transactions and many threads, and that this severely restricts the scalability of log-based HTMs.  ...  Moreover, we propose a novel design, where the store buffer is used to perform lazy version management (similar to Rock [12]) but overflowed transactions execute with a fallback log-based HTM that uses  ...  Overflow: When the buffer overflows, transactions have to be recovered via the software log. In order to avoid unnecessary aborts, our eager implementation creates the software log always.  ... 
doi:10.1145/1509084.1509094 fatcat:t3qtssordnh47i7db7yqusyssa

Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory

Lihang Zhao, Lizhong Chen, Jeffrey Draper
2014 2014 IEEE 28th International Parallel and Distributed Processing Symposium  
Hardware Transactional Memory (HTM) usually piggybacks onto the cache coherence protocol to detect data access conflicts between transactions.  ...  For the TM applications we studied, 41% of the transactional write requests incur false aborting.  ...  Note that the performance improvement is not necessarily proportional to the reduction in transaction aborts.  ... 
doi:10.1109/ipdps.2014.69 dblp:conf/ipps/ZhaoCD14 fatcat:cflgqa7jc5bxrfjyd7tn5mwm5a

An HTM-based update-side synchronization for RCU on NUMA systems

SeongJae Park, Paul E. McKenney, Laurent Dufour, Heon Y. Yeom
2020 Proceedings of the Fifteenth European Conference on Computer Systems  
Micro-bench-marks on a NUMA system having 144 hardware threads show RCX has up to 22.6 times better performance and up to 145 times lower HTM abort rates compared to a state-of-the-art RCU/HTM combination  ...  Read-copy update (RCU) can provide ideal scalability for read-mostly workloads, but some believe that it provides only poor performance for updates.  ...  Because RCU, RCU-HMCS, and RLU do not use HTM at all, the variants always show 0% abort rates. Figure 9 . 9 Performance of realistic workloads on modified virtual memory systems.  ... 
doi:10.1145/3342195.3387527 dblp:conf/eurosys/ParkMDY20 fatcat:l3lo6xnmdfe5vlgeyfcmzmn2im

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Adria Armejach, Azam Seyedi, Ruben Titos-Gil, Ibrahim Hur, Adri´n Cristal, Osman S. Unsal, Mateo Valero
2011 2011 International Conference on Parallel Architectures and Compilation Techniques  
Current HTM implementations, for both eager and lazy version management schemes, suffer from performance penalties due to the inability to handle two versions of the same logical data efficiently.  ...  We describe how the RDC can support both eager and lazy HTM systems, and we present two RDC-HTM designs.  ...  However, Eager-RDC-HTM improves the performance of such applications significantly, being closer to ideal.  ... 
doi:10.1109/pact.2011.67 dblp:conf/IEEEpact/ArmejachSGHCUV11 fatcat:iu6yttgvdjfcjbevcyuik3x344

Hybrid Transactional Memory Revisited [chapter]

Wenjia Ruan, Michael Spear
2015 Lecture Notes in Computer Science  
It does so via a novel state machine that maximizes the use of hardware TM, while affording opportunity to enforce fairness policies.  ...  ← ∅ 15 tx state ← N O 16 return 17 else xabort(38) 18 // STx couldn't commit via HTM.  ...  Configurations differ in terms of the range of keys present in the tree, and the ratio of lookups to inserts and removes (insert and remove operations are always performed in equal amounts).  ... 
doi:10.1007/978-3-662-48653-5_15 fatcat:kjdyxo25sjgnfkfq7omrr332xi

A survey on optimizations towards best-effort hardware transactional memory

Zhenwei Wu, Kai Lu, Ruibo Wang, Wenzhe Zhang
2020 CCF Transactions on High Performance Computing  
Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as  ...  Research efforts about joint usage of HTM and non-volatile memory (NVM) are also discussed.  ...  Acknowledgements The authors would like to thank the anonymous reviewers for their valuable comments and suggestions to improve the quality of the paper.  ... 
doi:10.1007/s42514-020-00049-2 fatcat:lf5s3agulfhpzgxcjgjk2msqfy

Fast in-memory transaction processing using RDMA and HTM

Xingda Wei, Jiaxin Shi, Yanzhe Chen, Rong Chen, Haibo Chen
2015 Proceedings of the 25th Symposium on Operating Systems Principles - SOSP '15  
We further build an efficient hash table for DrTM by leveraging HTM and RDMA to simplify the design and notably improve the performance.  ...  ., RDMA and HTM) to improve latency and throughput by over one order of magnitude compared to state-of-the-art distributed transaction systems.  ...  via RDMA.  ... 
doi:10.1145/2815400.2815419 dblp:conf/sosp/WeiSCCC15 fatcat:uta2jo4otnfvlfsachf4xamgae
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