Filters








127 Hits in 5.9 sec

Adiabatic SRAM for Low Power Devices

Amit Saxena, Kshitij Shinghal, Deepti Shinghal
2017 International Journal of Recent Trends in Electrical & Electronics Engineering  
Several techniques have been proposed to manage power consumption of SRAM-based memory structures. In this paper a robust adiabatic SRAM is designed.  ...  The power consumption of SRAM varies widely depending on how frequently it is accessed and some ICs can consume many watts at full bandwidth.  ...  ACKNOWLEDGEMENT Authors give their sincere thanks to the monad university and acknowledge the constant motivation and guidance of research board of Monad University.  ... 
doi:10.7323/ijrte/v4_i2/03 fatcat:7ogbiy52pbbqxeg5lr6kmmindq

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Farshad Moradi, Sumeet Kumar Gupta, Georgios Panagopoulos, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy
2011 IEEE Transactions on Electron Devices  
Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher  ...  This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM.  ...  With the understanding of the device characteristics of AD FinFETs discussed in this section, let us now present AD-FinFET-based 6T SRAMs and evaluate their benefits over conventional FinFET 6T SRAMs.  ... 
doi:10.1109/ted.2011.2169678 fatcat:ob4nymdbbrc6bjduv4wqx642fe

Performance Evaluation of 14 nm FinFET-Based 6T SRAM Cell Functionality for DC and Transient Circuit Analysis

Wei Lim, Huei Chaeng Chin, Cheng Siong Lim, Michael Loong Peng Tan
2014 Journal of Nanomaterials  
As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases.  ...  The simulation of the SRAM model is carried out in HSPICE based on 14 nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate.  ...  Introduction Static random-access memory (SRAM) constitutes a large percentage of cell area in system on chip (SOC) designs due to high number of transistors for a single SRAM cell [1] .  ... 
doi:10.1155/2014/820763 fatcat:rxbi4ja7jjeylbbt52dohinuzi

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture [chapter]

Ajay Kumar Singh
2017 Field - Programmable Gate Array  
The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power.  ...  The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.  ...  The main programming technologies used in FPGAs are static random memory (SRAM), flash memory, and antifuse [2] [3] [4] [5] .  ... 
doi:10.5772/67257 fatcat:ff4zwex2ofacbbtiiun2xl2eem

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Kiryong Kim, Seong-Ook Jung
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Bit-interleaving, FinFET, low-voltage operation, static random access memory (SRAM).  ...  The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme.  ...  Index Terms-Bit-interleaving, FinFET, low-voltage operation, static random access memory (SRAM). I.  ... 
doi:10.1109/tvlsi.2015.2450500 fatcat:med52kr64bau3cdh6xe452djde

A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability-Aware Design Optimization

Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto
2019 IEEE Journal of the Electron Devices Society  
area penalty and performance degradation to the base SRAM cell.  ...  A feasibility study on Ferroelectric Shadow SRAMs (FE-SRAMs) was performed using circuit simulations.  ...  To overcome the limitations of Flash memories, various alternatives, such as magneto-resistive random access memory (MRAM), phasechange random access memory (PRAM), and resistive random access memory (  ... 
doi:10.1109/jeds.2019.2949564 fatcat:ovnumivfrzccdkd2svxbrqgrxq

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

Jeren Samandari-Rad, Richard Hughey
2016 IEEE Access  
variations (PVT), electromigration (EM), negative bias temperature instability (NBTI), and soft-errors, among others] on top of deploying the most recent state of the art effective mitigation techniques  ...  minimize and predict the power/energy and power/energy variability of a 16-nm 6T-SRAM under the influence of the three major types of variations: Fabrication, Operation, and Implementation.  ...  OVERVIEW OF OUR MODEL A. SRAM The six-transistor-cell static random access memory (6T-SRAM) ( Fig. 1) is the conventional choice for most onchip memory designs.  ... 
doi:10.1109/access.2016.2521385 fatcat:vowwzjai7jhg3iezcclnpdph3e

Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations

G. V. Luong, S. Strangio, A. T. Tiedemann, P. Bernardy, S. Trellenkamp, P. Palestri, S. Mantl, Q. T. Zhao
2018 IEEE Journal of the Electron Devices Society  
Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability.  ...  A half SRAM cell with strained Si nanowire complementary tunnel-FETs (TFETs) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs.  ...  The static-random-access-memory (SRAM) cell, being one of the most important digital building block widely used as data caches in processors, is an important circuit vehicle to assess the advantages of  ... 
doi:10.1109/jeds.2018.2825639 fatcat:rqlmqkb7vzhcbfbborr2phqi4m

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors

Yunfei Gu, Dengxue Yan, Vaibhav Verma, Pai Wang, Mircea Stan, Xuan Zhang
2018 Journal of Low Power Electronics and Applications  
In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations  ...  While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/jlpea8030028 fatcat:ny4cuxcc2nhyvnltui7md6wnmu

Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Tara Ghafouri, Negin Manavizadeh
2020 Alexandria Engineering Journal  
Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing  ...  This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node.  ...  Moreover, employing multi-gate devices such as regular and negative capacitance fin field-effect transistors (FinFETs) in SRAM cells has contributed to reducing leakage power [3] .  ... 
doi:10.1016/j.aej.2020.06.026 fatcat:dmx3zawiuvarlc7rmui7vsjttu

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

Jeren Samandari-Rad, Matthew Guthaus, Richard Hughey
2014 IEEE Access  
In this paper, we develop methods for robust and resilient six-transistor-cell static random access memory (6T-SRAM) designs that mitigate the effects of device and circuit parameter variations.  ...  Furthermore, we illustrate and discuss other important reliability and performance issues such as supply voltage (Vdd) fluctuations, static-noise margin (SNM) reduction, soft errors impact, Negative Bias  ...  The six-transistor-cell static random access memory (6T-SRAM) ( Fig. 1) is the conventional choice for most on-chip memory designs.  ... 
doi:10.1109/access.2014.2323233 fatcat:hsqprvcb2zhalegj2gtletna7e

Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation

Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
2013 IEEE transactions on nanotechnology  
This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (V  ...  Our results indicate that UTB SOI 6T SRAM cell using low V th devices (|V th | = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise  ...  The bit-line length and capacitance are calculated based on the actual layout of a 65-nm 6T SRAM cell.  ... 
doi:10.1109/tnano.2011.2105278 fatcat:jacr7gqikvhpnoxrre3ougxd2u

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Behzad Ebrahimi, Reza Asadpour, Ali Afzali-Kusha, Massoud Pedram
2015 International journal of circuit theory and applications  
Schematics of (a) a conventional 6-T SRAM cell with nMOS access and precharged bitlines (AXN) and (b) the proposed SRAM cell with pMOS access and predischarged bitlines (AXP). B. EBRAHIMI ET AL.  ...  In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented.  ...  A summary of important parameters of the cells is given in Table II. 6. CONCLUSION In this work, we proposed a SRAM cell structure based on pMOS access transistors and predischarged bitlines.  ... 
doi:10.1002/cta.2057 fatcat:6njhvoonbrabfjg5ayatmvd6uy

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2010 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
and operation speed of a single-ended read/write 8 T SRAM cell.  ...  The test chip measurement results show that at 0.2 V V DD , an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 W. Index Terms-Low power, low voltage, single-ended SRAM.  ...  A bit-line usually has a very heavy capacitance loading. Every time a Read/Write operation is performed, the switching of bit-line costs significant power consumption.  ... 
doi:10.1109/tcsi.2010.2071690 fatcat:edhuaxhrunfnha3cgymgmu3shi

An Ultra-low-power Static Random-Access Memory Cell Using Tunneling Field Effect Transistor

2020 International Journal of Engineering  
The proposed SRAM TFET cell architecture achieves low power dissipation and attains high performance as compared to the CMOS and FINFET.  ...  This work evaluates the potential of TFET which can replace MOSFET due to the improved performance with low-power consumption, high speed, low sub-threshold slope, and supply voltage (VDD = 0.2 V).  ...  PROPOSED TUNNEL FIELD EFFECT TRANSISTOR BASED STATIC RANDOM-ACCESS MEMORY DESIGN Static Random-Access Memory (SRAM) is a volatile semiconducting memory, which is used to store on condition without periodic  ... 
doi:10.5829/ije.2020.33.11b.13 fatcat:xwtkki4zjfgodltsm3bcj6vzje
« Previous Showing results 1 — 15 out of 127 results