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Local reconfiguration for simultaneous coverage and tracking in a large scale camera network

Bryan Lemon, Vinod Kulathumani
2011 2011 IEEE International Conference on Technologies for Homeland Security (HST)  
We evaluate the performance of our algorithm in simulation and demonstrate that local reconfiguration is sufficient for maintaining an acceptable coverage of target and non-target points.  ...  Our algorithm requires only a local exchange of information, is quick to converge and ensures longer periods of stability between successive reconfiguration steps.  ...  We evaluated the performance of our algorithm in simulations and analyzed the impact of network density and the size of the area over which the reconfiguration is performed on the achievable coverage resolution  ... 
doi:10.1109/ths.2011.6107857 fatcat:mixamq5vznhmjbvgr7fpi3maee

A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual Processing

Nao Iwata, Shingo Kagami, Koichi Hashimoto
2007 2007 International Conference on Field-Programmable Technology  
To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network  ...  This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing.  ...  As an existing example of employing a dynamically reconfigurable processor for high-speed vision processing, implementation of connected component labeling using the DAPDNA-2 processor [9] is notable  ... 
doi:10.1109/fpt.2007.4439276 dblp:conf/fpt/IwataKH07 fatcat:6rt5elg4zbfu3omg6vn5knpf4y

Introduction to the special section on dependable network computing

D.R. Avresky, J. Bruck, D.E. Culler
2001 IEEE Transactions on Parallel and Distributed Systems  
His research addresses parallel computer architecture, parallel programming languages, and high performance communication structures.  ...  He is well-known for his work on internet infrastructure, Networks of Workstations (NOW), Active Messages, Split-C, the Threaded Abstract Machine (TAM), and dataflow systems.  ...  The paper "A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks" describes an approach to dynamically reconfiguring the routing in a irregular-topology LAN comprising  ... 
doi:10.1109/tpds.2001.910865 fatcat:kg2iu6fivve4loqitpfuqjkkcy

Survey on Coarse Grained Reconfigurable Architectures

Vaishali Tehre, Ravindra Kshirsagar
2012 International Journal of Computer Applications  
Performances both in terms of processing speed and power consumption are becoming more and more challenging in SOC designing.  ...  Hence a lot of research is going on to implement CGRA in SOC because Coarse-grained reconfigurable architecture can provide both performance and flexibility.  ...  Maximum of the work in reconfigurable area has focused on the efficient design with respect to system performance and compiler.  ... 
doi:10.5120/7429-0104 fatcat:nb5kpk3ja5g2dlilbeudebl77a

Author Index

2008 2008 IEEE International Symposium on Parallel and Distributed Processing  
a Long-Life Pervasive System Trehan, Amitabh Picking up the Pieces: Self-Healing in Reconfigurable Networks Trendelenburg, Stanis A Rapid Prototyping Environment for High-speed Reconfigurable Analog Signal  ...  Achieving and Assuring High Availability Gu, Bo A Locally-Optimizing Approach for Multichannel Assignment and Routing Gu, Yi Optimizing Network Performance of Computing Pipelines in Distributed Environments  ... 
doi:10.1109/ipdps.2008.4536576 fatcat:7unikf5ywjhjtdd6xtrmcom3gq

Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs

Christian Schuck, Bastian Haetzer, Jürgen Becker
2011 International Journal of Reconfigurable Computing  
The created speed maps of the FPGA area can be used as an input for the dynamic frequency scaling. Figures for reconfiguration performance and power savings are given.  ...  Such systems cannot take the full advantage of partial and dynamic self-reconfiguration.  ...  All advantages of the high-speed clock distribution network could be maintained.  ... 
doi:10.1155/2011/671546 fatcat:iwsfqklv7fe2ni7d2jwbbn4hni

Flexible and distributed real-time control on a 4G telecom MPSoC

Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
This MPSoC platform is built with telecom baseband processors interconnected with a Network-on-Chip. The control is performed by a MIPS processor embedded in each baseband processor.  ...  This control processor can locally reconfigure and schedule the applications with real-time telecom constraints.  ...  This innovative approach in the context of hard real-time and high complexity is evaluated in terms of performance and power consumption on a modem LTE application.  ... 
doi:10.1109/iscas.2010.5537660 dblp:conf/iscas/JalierLSBT10 fatcat:4i5ldhvk7nhm3ghg2mlxmo3xdu

Providing personalized converged services based on flexible network reconfiguration

YuXiang Hu, JuLong Lan, JiangXing Wu
2011 Science China Information Sciences  
Our evaluation shows that reconfigurable router is transparent for upper service-providing networks and results in little performance impact on the service delivery when both hardware and software reconfiguration  ...  In addition, to demonstrate the generality of our model, we provide a prototype of reconfigurable router.  ...  Evaluation In this section, we evaluate the performance of service network reconfiguration using reconfigurable routers.  ... 
doi:10.1007/s11432-010-4165-8 fatcat:m6ludgwnebhstmujzrf72i24de

DESIGN AND IMPLEMENTATION OF NOVEL NOC ARCHITECTURE ON FPGA

ShilpaK Gowda, RekhaK R, NatarajK R
2018 International Journal of Advanced Research  
Previous work:-Lot of work has been carried out in the field of NoC to achieve high performance network with high efficiency.  ...  Due to present architecture limitations such as high area it is very difficult to support for dynamically reconfigurable designs. dynamically placed on chip for FPGA based reconfigurable network devices  ... 
doi:10.21474/ijar01/7003 fatcat:wtjdcxeiyfg7hfrspj5wmdrcmy

A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology

Toru Katagiri, Hideharu Amano
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
Although dynamically reconfigurable processor arrays (DR-PAs) are advantageous for embedded devices because of their high energy efficiency, many of the recent mobile devices are required to execute increasingly  ...  just a small increase of area and power consumption.  ...  The behavior of PEs and the connection between PEs are dynamically reconfigured in accordance with hardware contexts read from context memories, and dynamic reconfiguration can be performed in either one  ... 
doi:10.1109/fpl.2014.6927438 dblp:conf/fpl/KatagiriA14 fatcat:qrbuogo6d5bnxgoamtutos54be

Review of recent trends in Coarse Grain Reconfigurable Architectures for signal processing applications

Sridharan M.., R. Ramya
2018 Advances in Systems Science and Applications  
As the complexity of algorithms increases, a matching improvement in speed performance of the hardware becomes essential to maintain the quality of service.  ...  Reconfigurable hardware architecture is proposed as a possible alternative in this regard.  ...  Also shown that a 2X improvement in speed performance is achieved by duplication based on dynamic composition.  ... 
doi:10.25728/assa.2018.18.1.508 fatcat:eihxjjbe5fbtfidecoa4j7sv6y

Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

Julio Dondo Gazzano, Francisco Sanchez Molina, Fernando Rincon, Juan Carlos López
2015 The Scientific World Journal  
This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs.  ...  However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the  ...  The configuration of each dynamic area is performed by the configuration kernel component.  ... 
doi:10.1155/2015/272536 pmid:25874241 pmcid:PMC4385699 fatcat:rrfxbkyrzfhu3df2qagz37vcle

On-FPGA Communication Architectures and Design Factors

Terrence T. Mak, Pete Sedcole, Peter K. Cheung, Wayne Luk
2006 2006 International Conference on Field Programmable Logic and Applications  
These platforms require high-performance on-chip communication architectures for efficient and reliable inter-processor communication.  ...  In this paper, we survey the state-of-the-art on-FPGA communication architectures and methodologies.  ...  The PLB is a high-speed and high-bandwidth bus.  ... 
doi:10.1109/fpl.2006.311209 dblp:conf/fpl/MakSCL06 fatcat:xmwjluwdpva4bnm2abhitvtvce

A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

John C. Hoffman, Marios S. Pattichis
2011 International Journal of Reconfigurable Computing  
Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR.  ...  Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance.  ...  Acknowledgments The authors would like to acknowledge the support of the Xilinx Corporation for this research.  ... 
doi:10.1155/2011/439072 fatcat:sislyduj5rcbhklbing5skupji

Prospective of Fifth Generation Mobile Communications

Anwar M Mousa
2012 International Journal of Next-Generation Networks  
core and a single fully reconfigurable terminal able to autonomously operate in different heterogeneous access networks is proposed.  ...  It also reviews in brief the evolution of wireless and cellular systems focusing on four main key factors: radio access, data rates, bandwidth and switching schemes in addition to change in network architecture  ...  In addition to the cellular systems, current wireless technologies include Wireless Local Area Networks (WLAN) 802.11 [7] and Wireless Metropolitan Area Networks (WMAN) 802.16 [8] .  ... 
doi:10.5121/ijngn.2012.4302 fatcat:44tjkxfakbchhnwsvkroqoqttu
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