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Efficient arithmetic on ARM-NEON and its application for high-speed RSA implementation

Hwajeong Seo, Zhe Liu, Johann Großschädl, Howon Kim
2016 Security and Communication Networks  
Advanced modern processors support Single Instruction Multiple Data (SIMD) instructions (e.g.  ...  Intel-AVX, ARM-NEON) and a massive body of research on vector-parallel implementations of modular arithmetic, which are crucial components for modern public-key cryptography ranging from RSA, ElGamal,  ...  As length of operand increases, the performance enhancements decrease but we still have high improvements in 8192-bit by 20 ∼ 24% and 23 ∼ 35%, respectively.  ... 
doi:10.1002/sec.1706 fatcat:ussrhv32szgible42zoywgne6y

SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core

Nehir Sonmez, Arda Yurdakul
2006 2006 International Symposium on System-on-Chip  
The flexible SISD core with general-purpose instructions fits on small FPGAs, but can be easily configured to incorporate application-specific instructions and to operate in SIMD mode when higher performance  ...  In this study, an FPGA-based, configurable, application-specific, SIMD-capable, non-pipelined RISC soft processor core that operates on variable-width fixed-point data is presented.  ...  The architecture of these processors is usually SISD (Single Instruction-Single Data).  ... 
doi:10.1109/issoc.2006.321990 dblp:conf/issoc/SonmezY06 fatcat:icjvxnehdfhk3av63egqlfablq

Perspective Study and Analysis of Parallel Architecture

Varsha Thakur, Sanjay Kumar
2016 International Journal of Computer Applications  
This paper presents a thorough survey of the parallel architecture and performane is analysed on the basis of the execution time of few parallel sorting algorithms in multicore processors .To implement  ...  Parallel architecture is those that emphasize on parallel and concurrent computation among different processors.  ...  Some parallel architecture are designed with small number of PEs of complex internal circuitry to enhance the overall performance of the architecture.  ... 
doi:10.5120/ijca2016911285 fatcat:nbnylap6izgyfmzshewet6whla

Scheduling on Heterogeneous Multi-core Processors Using Stable Matching Algorithm

Muhammad Rehman, Muhammad Asfand-e-Yar
2016 International Journal of Advanced Computer Science and Applications  
The primary objective of this study is to improve the dynamic selection of the processor core to fulfill the power and performance requirements using a task scheduler.  ...  The tasks to core mapping is performed on the basis of priorities of the tasks and cores.  ...  The main objective of scheduling tasks by employing these techniques was to save energy and enhance throughput.  ... 
doi:10.14569/ijacsa.2016.070666 fatcat:2vc2nstvjzhczo2umugdti2oa4

Page 191 of Journal of Chemometrics Vol. 2, Issue 3 [page]

1988 Journal of Chemometrics  
EVALUATION OF COMPUTING CAPABILITIES 191 multiplicity of instruction streams and data streams in a computing system;'’ both the PDP 11/34A and PRIME 9955 are SISD (single instruction, single data) while  ...  Here an instruction stream is a sequence of instructions executed by a single processor; a data stream is a sequence of data called for by the instruction stream.  ... 

Observations on Power-Efficiency Trends in Mobile Communication Devices [chapter]

Olli Silvén, Kari Jyrkkä
2005 Lecture Notes in Computer Science  
In this paper, we explain some of the observed developments.  ...  So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1007/11512622_16 fatcat:y657ek2c3ve5pjsnm5d2bouq6m

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
In this paper, we explain some of the observed developments.  ...  So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1155/2007/56976 fatcat:qaf74xxzdjf6bcrwxxkhvqsqlm

Observations on Power-Efficiency Trends in Mobile Communication Devices

Olli Silven, Kari Jyrkkä
2007 EURASIP Journal on Embedded Systems  
In this paper, we explain some of the observed developments.  ...  So far, the improvements of the silicon processes in mobile phones have been exploited by software designers to increase functionality and to cut development time, while usage times, and energy efficiency  ...  Acknowledgements This paper is based on the contributions of numerous people. In particular, we wish to thank Dr. Lauri Pirttiaho and Prof. Yrjö Neuvo, both from the Nokia Corporation.  ... 
doi:10.1186/1687-3963-2007-056976 fatcat:4vu54id7nfdjtdbohhkyr7p55e

Very high-speed computing systems

M.J. Flynn
1966 Proceedings of the IEEE  
"Stream," as nsed here, refers to the sequence of data or irstructiom as seen by the machine daring tbe execution of a program. m e coastitaeats of a system :storage, exeation, and h t r u d o n bandhg  ...  Very high-speed computers may be clnssified as follows: 1) Single Jktmction S t r d i n g l e Data Stream (SISD) 2) S i l e Imbnctioa Stream-Multiple Data Stream (SIMD) 3) Multiple hstmcth StrePntSingle  ...  Aschenbrenner of the Argonne National Laboratory for several valuable discussions on some of the material.  ... 
doi:10.1109/proc.1966.5273 fatcat:5ankvvfruvd37obh4zfgwrhppm

Architecture and Design of Micro Knowledge and Micro Medical Processing Units

Shawon S. M. Rahman, Syed V. Ahamed
2017 International journal of network security and its applications  
In this article, we briefly present the evolution of conventional processor over the last four decades as a prelude to the evolution of knowledge processors.  ...  The design of such chipsets permits the micro knowledge processor unit (µkpu) lodged in a generic knowledge machine to "understand" the context of the problem in reference to the global knowledge of such  ...  Figure 2 : 2 Representation of a Single Instruction Single Data (SISD) Processor of a typical computer that Figure 3 : 3 Simplified representation of a Single Process Single Object (SPSO) Processor  ... 
doi:10.5121/ijnsa.2017.9501 fatcat:unsvvsfo5fh35fjd43jxg6p4zi

An Efficient, Self-Contained, On-chip Directory: DIR1-SISD

Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2015 2015 International Conference on Parallel Architecture and Compilation (PACT)  
DIR1-SISD keeps track of a single -private-owner, or allows multiple-readers-multiple-writers to exist simultaneously by transferring the responsibility for their coherence to the corresponding cores.  ...  thus avoiding the complexities of broadcasts) and without the need to have a backing store.  ...  Figure 3 . 3 Logical organization of Dir1 1 -SISD directory. Figure 4 .Figure 5 . 45 Dir 1 -SISD performance comparison. Results are normalized to MESI protocol.  ... 
doi:10.1109/pact.2015.23 dblp:conf/IEEEpact/DavariRHK15 fatcat:yhyrbyue6jbznkfqam6ibep3eq

Evaluation of computing capabilities of a hierarchy of mini-to-supercomputers: Applications to ion microscopic analysis

Yong-Chien Ling, Dan N. Bernardo, George H. Morrison
1988 Journal of Chemometrics  
Furthermore, with the advent of vector and parallel processors, a single instruction might perform a large number of floating-point operations.  ...  Also, in the case of image smoothing operation, increasing n will enhance the noise cleaning effect (but at the expense of degrading feature sharpness).  ... 
doi:10.1002/cem.1180020304 fatcat:36hql6go25cy3ekesvg7gicbd4

Towards the Optimal Hardware Architecture for Computer Vision [chapter]

Alejandro Nieto, David Lpez, Vctor Brea
2012 Machine Vision - Applications and Systems  
The kind of computation performed at this stage is so varied that the best option is often a general purpose SISD processor.  ...  However, despite the evolution of the industry pure SISD microprocessors do not offer adequate performance for a large set of tasks.  ... 
doi:10.5772/34023 fatcat:higcvn5ffrhzlieberxwiatasa

Performance Enhancement Of Motion Estimation Using Sse2 Technology

Trung Hieu Tran, Hyo-Moon Cho, Sang-Bock Cho
2008 Zenodo  
In this paper, the performance of motion estimation is enhanced by using Intel's Streaming SIMD Extension 2 (SSE2) technology with Intel Pentium 4 processor.  ...  Therefore, the timing constraints for running these motion estimation algorithms not only challenge for the video codec but also overwhelm for some of processors.  ...  In this paper, we present the performance enhancement of motion estimation algorithms by using the Streaming SIMD Extensions 2 (SSE2) with Intel Pentium 4 processors.  ... 
doi:10.5281/zenodo.1327908 fatcat:4s7xheqeszdj7hgzicft64iaeu

A Parallel Processing Technique Based on GMO and BCS for Medical Image Encryption

2020 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
The enhancement of this GMO and BCS based encryption are also given here by using the parallel implementation of the algorithm.  ...  The binary bit values of pixels of the initial Image are rotated circularly to generate a new binary bit value of pixels encrypted image.  ...  ACKNOWLEDGEMENT A lot of thanks to Ophthalmologist (eye specialist) Dr.  ... 
doi:10.35940/ijitee.c9044.019320 fatcat:sm7kvyydlzhilkevs7isynjuc4
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