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Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries

Qing Xie, Xue Lin, Yanzhi Wang, Shuang Chen, Mohammad Javad Dousti, Massoud Pedram
2015 IEEE Transactions on Circuits and Systems - II - Express Briefs  
This paper builds standard cell libraries for an advanced 7nm FinFET technology, supporting multiple threshold voltages and supply voltages.  ...  Circuit synthesis results of various combinational and sequential circuits based on presented 7nm FinFET standard cell libraries forecast 10X and 1000X energy reductions on average in the super-threshold  ...  Acknowledgements: The authors would like to thank Woojoo Lee and Ji Li for helping with the generation of simulation data.  ... 
doi:10.1109/tcsii.2015.2391632 fatcat:n4ec75pwubgkncol2edljifz64

FinFET Circuit Design [chapter]

Prateek Mishra, Anish Muttreja, Niraj K. Jha
2010 Nanoelectronic Circuit Design  
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices.  ...  ) at 22-nm and beyond, offer interesting delay-power tradeoffs.  ...  The relationship between the corresponding values of off-current I H off and I L off , respectively, is evident in Fig. 7 7 Simulated I ds ÀV gs characteristics for an overdriven 32 nm n-type FinFET  ... 
doi:10.1007/978-1-4419-7609-3_2 fatcat:nl33ampqhzdfvkil6gf42tyj3y

Comparative soft error evaluation of layout cells in FinFET technology

L. Artola, G. Hubert, M. Alioto
2014 Microelectronics and reliability  
This work presents a comparative soft error evaluation of logic gates in bulk FinFET technology from 65-down to 32-nm technology generations.  ...  Good agreement between the calculated transient current, and TCAD mixed-mode simulations is demonstrated.  ...  From a design standpoint, the improvement of the reliability requires the accurate estimate of the SE susceptibility of FinFET standard cell libraries, in order to support the optimization of cells during  ... 
doi:10.1016/j.microrel.2014.07.109 fatcat:e2nrf7kj2zaf5h5oo6djefvoea

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Animesh Datta, Ashish Goel, Riza Tamer Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Results show about 8.5% area savings and 18% power savings over conventional FinFET technology for ISCAS85 benchmark circuits in 45-nm technology with no performance penalty.  ...  An efficient circuit synthesis methodology comprised of proposed low-power logic options in FinFET design library has been developed.  ...  can be used for direct replacement of conventional bulk CMOS devices in the standard CMOS circuit design. 2) 4-T FinFET: FinFETs with isolated gates and separate gate contacts result in four-terminal  ... 
doi:10.1109/tcad.2007.896320 fatcat:txip2l4fgzg4dnwesim2ym7aim

FinFETs: From Devices to Architectures

Debajit Bhattacharya, Niraj K. Jha
2014 Advances in Electronics  
Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus  ...  We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs.  ...  CCF-1217076 and CCF-1318603.  ... 
doi:10.1155/2014/365689 fatcat:wj3mk6blenfwtesg43n5qfevfq

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

Usman Khalid, Antonio Mastrandrea, Mauro Olivieri
2015 Microelectronics and reliability  
In this work, we calculated and compared the effect of process variations and NBTI aging over the years on the actual WNM of various CMOS and FinFET based flip-flop cells.  ...  The assessment of noise margins and the related probability of failure in digital cells has growingly become essential, as nano-scale CMOS and FinFET technologies are confronting reliability issues caused  ...  The target technology models are a bulk FinFET 16 nm LSTP process, at nominal 0.85V supply VDD, and a bulk CMOS 16 nm HP process, the latter with scaled-up supply VDD from nominal 0.7V to 0.85V in order  ... 
doi:10.1016/j.microrel.2015.07.050 fatcat:2gqltxvy5rd33ew5552kmpi5wm

Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach

Ming-Long Fan, Yu-Sheng Wu, Vita Pi-Ho Hu, Chien-Yu Hsieh, Pin Su, Ching-Te Chuang
2011 IEEE Transactions on Electron Devices  
For half-selected cells on the selected bit line, a sufficient margin is observed between WRITE time (for selected cells) and WRITE disturb (for half-selected cells).  ...  This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating  ...  ACKNOWLEDGMENT The authors would like to thank the National Center for High-Performance Computing in Taiwan for the use of computational facilities and software.  ... 
doi:10.1109/ted.2010.2096225 fatcat:d5sq5hrrufhdpiqqt3uyraktwm

Back to the Future: Digital Circuit Design in the FinFET Era

Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, Mircea R. Stan
2017 Journal of Low Power Electronics  
In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology  ...  Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices.  ...  Acknowledgments: This work was supported by NSF grants CCF 1619127 and CCF 1543837, by DARPA under the UPSIDE and PERFECT programs and by the Center for Future Architecture Research (C-FAR), one of six  ... 
doi:10.1166/jolpe.2017.1489 fatcat:b5nc5b3rajb6bf6zmsrtz63tby

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Jian Zhang, Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
-nm low-standby-power FinFET technology.  ...  Synthesis results of ISCAS'85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22  ...  IV PERFORMANCE OF GATES WITH TIG SINWFET AND LSTP FINFET Fig. 17. Comparison results of logic gates with TIG SiNWFET and FinFET. functions are not included in the FinFET library.  ... 
doi:10.1109/tcsi.2014.2333675 fatcat:hxvcujvqobdw7p6gl3wutqwvse

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices

Alireza Shafaei, Yanzhi Wang, Xue Lin, Massoud Pedram
2014 2014 IEEE Computer Society Annual Symposium on VLSI  
Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power  ...  Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5× (9×) and 11× (24×) reduction in read energy and area, respectively.  ...  ACKNOWLEDGMENT This research is supported by grants from the PERFECT program of the Defense Advanced Research Projects Agency and the Software and Hardware Foundations of the National Science Foundation  ... 
doi:10.1109/isvlsi.2014.94 dblp:conf/isvlsi/ShafaeiWLP14 fatcat:qmop5naairfddcpxelbg5yltbi

Key characterization factors of accurate power modeling for FinFET circuits

KaiSheng Ma, XiaoXin Cui, Kai Liao, Nan Liao, Di Wu, DunShan Yu
2014 Science China Information Sciences  
Based on the simulation result, standard cell power library model for FinFET is proposed.  ...  Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm  ...  in conventional bulk CMOS.  ... 
doi:10.1007/s11432-014-5169-6 fatcat:oqhjxpsovjarjehcotujwcsfpa

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish H., Shashikumar D.
2016 Communications on Applied Electronics  
Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and  ...  However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number.  ...  The prime difference between the conventional planar CMOS and FinFET is actually the fin, which is responsible for furnishing the channel for propagating the current in the switched on stage of the device  ... 
doi:10.5120/cae2016652312 fatcat:hhmxwgzi7ffsjme2jpvbis4fom

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Rafael N. M. Oliveira, Cristina Meinhardt
2020 Journal of Integrated Circuits and Systems  
Thus, in this work, weevaluate the influence of nine XOR topologies on the radia-tion robustness, discussing the influence of logic family, the de-vice technology and environment factors as temperature  ...  The de-pendence of temperature aggressively impact the FinFET tech-nology devices operating at near-threshold.  ...  ACKNOWLEDGEMENTS This work was financed in part by National Council for Scientific and Technological Development CNPq and the Propesq/UFSC.  ... 
doi:10.29292/jics.v15i2.131 fatcat:nxkjgwzxf5ht7e7sweyi6256vy

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

M Rostami, K Mohanram
2011 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.  ...  in comparison to conventional FinFET gates.  ...  Jha at Princeton University, Princeton, NJ, for helpful discussions and suggestions over aspects of FinFET TCAD simulation. They thank M.  ... 
doi:10.1109/tcad.2010.2097310 fatcat:eppkmuoipngsdhiomzyxqfm26q

Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices

A. Bansal, B.C. Paul, K. Roy
2005 IEEE Transactions on Electron Devices  
for direct replacement of conventional bulk CMOS devices in the standard CMOS circuit design. 2) 4-T FinFET: FinFETs with isolated gates and separate gate contacts result in four-terminal devices.  ...  FinFET-Device-Based Circuit Synthesis Initially, both the standard cell design libraries (i.e., 3-T library and Extended library) are developed and compiled with the Synopsys Library Compiler.  ...  /FinFET devices, for high-performance logic and memory applications.  ... 
doi:10.1109/ted.2004.842713 fatcat:ki5vlrqvczegnnbc6kuszrxzky
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