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ARCHITECT-R

R. A. Gonçalves, P. A. Moraes, J. M. P. Cardoso, D. F. Wolf, M. M. Fernandes, R. A. F. Romero, E. Marques
2003 Proceedings of the 2003 ACM symposium on Applied computing - SAC '03  
Current approaches often involve the design and implementation of hardwired solutions, with the associated problems of a long development cycle and inflexibility.  ...  In this paper we present a framework called ARCHITECT-R, which aims to design and program specialized hardware for robots based on FPGAs.  ...  The output of the ARCHITECT-R framework is a combination of an embedded processor, RPUs, and peripherals.  ... 
doi:10.1145/952660.952665 fatcat:lvrwtwok7zgnlkd6ahgkzwu6uu

ARCHITECT-R

R. A. Gonçalves, P. A. Moraes, J. M. P. Cardoso, D. F. Wolf, M. M. Fernandes, R. A. F. Romero, E. Marques
2003 Proceedings of the 2003 ACM symposium on Applied computing - SAC '03  
Current approaches often involve the design and implementation of hardwired solutions, with the associated problems of a long development cycle and inflexibility.  ...  In this paper we present a framework called ARCHITECT-R, which aims to design and program specialized hardware for robots based on FPGAs.  ...  The output of the ARCHITECT-R framework is a combination of an embedded processor, RPUs, and peripherals.  ... 
doi:10.1145/952532.952665 dblp:conf/sac/GoncalvesMCWFRM03 fatcat:listfpiarneifgpv3uu7tug2r4

Commodity clusters: performance comparison between PCs and workstations

R. Carter, J. Laroco, R. Armstrong
1996 Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing HPDC-96  
The size of the PC market is about nine times larger than the proprietary UNIX workstation market. Intel Pentium based systems are the performance leader in this market.  ...  1 Introduction Traditionally, the bulk of large scale scientific and engineering computations were performed on large specialized Supercomputers.  ...  At the time of this writing, 166 MHz Pentiums and 200 MHz Pentium Pros are standara leading to CPU performance increases of a Network The networks hosted on each node of the cluster are standard 10Mb/s  ... 
doi:10.1109/hpdc.1996.546199 dblp:conf/hpdc/CarterLA96 fatcat:2zejxhg4sjdedajszu4obw3eyq

Biological Data Modelling and Scripting in R [chapter]

Srinivasan Ramachandran, Rupanjali Chaudhuri, Srikant Prasad, Ab Rauf, Chaitali Paul, Shreya Chakraborty, Bhanwar Lal, Rahul Shubhra
2011 Systems and Computational Biology - Bioinformatics and Computational Modeling  
Data modeling for R Data modeling for R involves identification of the datasets required for the corresponding problem undertaken.  ...  R is maintained by a core group of experts, thus ensuring its availability for long life. R in its repository also has a number of packages useful in various fields of biology.  ...  On a typical workstation of 1GB RAM and Intel(R) Pentium(R) 4 CPU 3.40GHz, it takes about 5 hrs to complete a similarity search.  ... 
doi:10.5772/18627 fatcat:5okhtnduvjhcdeq4en4uflv25a

A case for intelligent RAM

D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, K. Yelick
1997 IEEE Micro  
Merging processing and memory into a single DRAM chip could revolutionize the semiconductor industry.  ...  In several processors, it has grown to 60% of the area and almost 90% of the transistors. 3 In fact, the Pentium Pro offers a package with two die, the larger being the 512-Kbyte second-level cache.  ...  Note the substantial increase in memory for the Mitsubishi M 32 R/D Organization of an IRAM vector processor design.  ... 
doi:10.1109/40.592312 fatcat:fkjx3bx5k5b7dhifh54c5vrmgu

3-D atomistic nanoelectronic modeling on high performance clusters: multimillion atom simulations

Gerhard Klimeck, Fabiano Oyafuso, R Chris Bowen, Timothy B Boykin, Thomas A Cwik, Edith Huang, Edward S Vinyard
2002 Superlattices and Microstructures  
The resulting sparse complex Hamiltonian matrix is of the order to tens of millions.  ...  The prototype development of a software tool that enables this class of simulation is presented.  ...  The supercomputer used in this investigation was provided by funding from the NASA Offices of Earth Science, Aeronautics, and Space Science.  ... 
doi:10.1006/spmi.2002.1038 fatcat:yc446kl7m5hdng2nql25n4ny7m

Analyzing the Effects of Hyperthreading on the Performance of Data Management Systems

Wessam M. Hassanein, Layali K. Rashid, Moustafa A. Hammad
2008 International journal of parallel programming  
This paper characterizes the performance of a prototype open-source DBMS running TPC-equivalent benchmark queries on an Intel Pentium 4 Hyper-Threading processor.  ...  We use hardware counters provided by the Pentium 4 to evaluate the micro-architecture and study the memory system behavior of each query running on the DBMS.  ...  [16] characterize the performance of Java applications on Intel Pentium 4 hyper-threading processors.  ... 
doi:10.1007/s10766-007-0066-x fatcat:ib756dz25zg6bpxpbyaw7qbtue

Can hardware performance counters be trusted?

Vincent M. Weaver, Sally A. McKee
2008 2008 IEEE International Symposium on Workload Characterization  
We collect retired instruction performance counter data from the full SPEC CPU 2000 and 2006 benchmark suites on nine different implementations of the x86 architecture.  ...  Comparing a tool's outputs against hardware performance counters on an actual machine is a common means of executing a quick sanity check.  ...  Again, the Pentium 4 counter is not affected by this, but all of the other processors are.  ... 
doi:10.1109/iiswc.2008.4636099 dblp:conf/iiswc/WeaverM08 fatcat:46qr7regkjdotbdlx3keafdueq

Green Support for PC-Based Software Router: Performance Evaluation and Modeling

R. Bolla, R. Bruschi, A. Ranieri
2009 2009 IEEE International Conference on Communications  
Our main objective is to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR networking performance and behavior.  ...  To this purpose, we separately characterized the roles of both HW and SW layers through a large set of internal and external experimental measurements, obtained with a heterogeneous set of HW platforms  ...  With this main aim, we performed several benchmarking sessions with a heterogeneous set of HW platforms, in order to carefully characterize the impact of power management mechanisms on SR performance.  ... 
doi:10.1109/icc.2009.5199050 dblp:conf/icc/BollaBR09 fatcat:idiknmxhjfc3rmtlefjbcw6qlq

Memory hierarchy considerations for cost-effective cluster computing

Xing Du, Xiaodong Zhang, Zhichun Zhu
2000 IEEE transactions on computers  
We present an analytical model for evaluating the performance impact of memory hierarchies and networks on cluster computing.  ...  Different types of applications are characterized by parameterized workloads with different computation and communication requirements. The model has been validated by simulations and measurements.  ...  ACKNOWLEDGMENTS We appreciate the discussions with J. Ding of Intel on the Pentium processor architecture.  ... 
doi:10.1109/12.869323 fatcat:izc5732aqfg43bgcjxusnyieji

Overview of research efforts on media ISA extensions and their usage in video coding

V. Lappalainen, T.D. Hamalainen, P. Liuha
2002 IEEE transactions on circuits and systems for video technology (Print)  
This paper summarizes the results of over 25 research groups or individual researchers that have presented video coding implementations on general-purpose processors with the new single instruction multiple  ...  Additionally, a performance comparison is given for four representative encoder implementations based on the reported results.  ...  The performance of Aphelium is based on optimizing the code for MMX and Intel P6 processor core, which is used in all Pentium processors since Pentium Pro.  ... 
doi:10.1109/tcsvt.2002.800865 fatcat:tf62dj6pozda5e2iqck6iipu2u

Decisive Aspects in the Evolution of Microprocessors

H. Falk
2004 Proceedings of the IEEE  
=6 6,0$ 0(0%(5 ,((( The incessant demand for higher performance has provoked a dramatic evolution of the microarchitecture of high performance microprocessors.  ...  We show that designers increased the throughput of the microarchitecture at the instruction level basically by the subsequent introduction of temporal, issue and intra-instruction parallelism in such a  ...  While L2 caches of previous models were coupled to the processor via the processor bus (for instance in the Pentium), recent high performance processors such as the Pentium Pro, Pentium II and Pentium  ... 
doi:10.1109/jproc.2004.837615 fatcat:3liaxjrdcje3rddzxtm52kagtu

A Network Processor-Based, Content-Aware Switch

Li Zhao, Yan Luo, L.N. Bhuyan, R. Iyer
2006 IEEE Micro  
SRAM versus DRAM T his article presents the latest results in our effort to enhance our NP-based contentaware switch. 15 Our future work includes pro-cessing all the TCP options in the network processor  ...  Moreover, switches based on general-purpose processors can't provide satisfactory performance, because of interrupt and moving packets over the peripheral component interconnect (PCI) bus.  ...  Her research interests include computer architecture, network computing, and performance evaluation. She is a member of the IEEE.  ... 
doi:10.1109/mm.2006.46 fatcat:erlzhnueavgdnl3zuig3d6wc3e

The history of the microprocessor

Michael R. Betker, John S. Fernando, Shaun P. Whalen
2002 Bell Labs technical journal  
Intel pushed Pentium performance further in 1996 with its superpipelined Pentium Pro.  ...  With many of the same features used by the RISC vendors, the Pentium Pro's integer performance was better than some of the RISC processors. Its floating-point performance lagged as it always had.  ... 
doi:10.1002/bltj.2082 fatcat:w2ilifumlzeotdhnncopefkxkm

Depth and Depth-Based Classification with R Package ddalpha

Oleksii Pokotylo, Pavlo Mozharovskyi, Rainer Dyckerhoff
2019 Journal of Statistical Software  
The R package ddalpha is a software directed to fuse experience of the applicant with recent achievements in the area of data depth and depth-based classification. ddalpha provides an implementation for  ...  Following the seminal idea of Tukey (1975) , data depth is a function that measures how close an arbitrary point of the space is located to an implicitly defined center of a data cloud.  ...  Acknowledgments The authors highly appreciate the help of Karl Mosler consisting in numerous remarks on earlier versions of this article and his notable contributions to the field of data depth.  ... 
doi:10.18637/jss.v091.i05 fatcat:7lqc4fnxjzf7tihrxnvnataqry
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