Filters








5,753 Hits in 5.9 sec

Towards 100G packet processing: Challenges and technologies

Christian Hermsmeyer, Haoyu Song, Ralph Schlenk, Riccardo Gemelli, Stephan Bunse
2009 Bell Labs technical journal  
The state-of-the-art architectures and algorithms for every aspect of packet processing are described.  ...  Ethernet (GbE) interfaces on their server stacks, asking for 100 GbE uplinks towards central switches and for multiple 100 GbE interfaces towards the point of presence.  ...  Acknowledgements We acknowledge gratefully that part of this work has been supported by the German Ministry for Research and Education (BMBF) under the EUREKA project "100GET-100Gbit/s Carrier-Grade Ethernet  ... 
doi:10.1002/bltj.20373 fatcat:nc5upq6ga5blnmnyuuy4r3hn6y

A High Speed Hardware Scheduler for 1000-Port Optical Packet Switches to Enable Scalable Data Centers

Joshua Lawrence Benjamin, Adam Funnell, Philip Michael Watts, Benn Thomsen
2017 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI)  
In this paper, we present a pipelined and highly parallel electronic scheduler that configures the high-radix (1000-port) optical packet switch.  ...  switch ASIC, with a clock period of less than 8ns, enabling 138 scheduling iterations to be performed in 1µs.  ...  Data centers today use electronic switch ASICs which are limited in capacity by the product of pin bandwidth and the number of high-speed signal pins [2] , which is only growing at a slow rate.  ... 
doi:10.1109/hoti.2017.22 dblp:conf/hoti/BenjaminFWT17 fatcat:czs4bgsxqjeg7gfoaoy5kogikq

Experimental demonstration of an ultra-low latency control plane for optical packet switching in data center networks

Paris Andreades, Kari Clark, Philip M. Watts, Georgios Zervas
2019 Optical Switching and Networkning Journal  
In this paper we present a high-speed control plane design based on a central switch scheduler for nanosecond optical switching which significantly reduces the end-to-end latency in the network compared  ...  However, further bandwidth scaling is limited by the number of high-speed signal pins on electronic chips [6] .  ...  The FPGA evaluation boards used in our experimental demonstration were provided by Xilinx.  ... 
doi:10.1016/j.osn.2018.11.005 fatcat:mnq4sidrrjfazfa6mdyplr5pta

Towards High-Performance Network Intrusion Prevention System on Multi-core Network Services Processor

Xiang Wang, Yaxuan Qi, Baohua Yang, Yibo Xue, Jun Li
2009 2009 15th International Conference on Parallel and Distributed Systems  
To resolve the problems and bottlenecks of high-speed processing, we investigate the main design aspects which have dramatic impacts on most parallel network security system implementations: efficient  ...  and flexible pipeline and parallel processing, flow-level packet-order preserving, and latency hiding of deep packet inspection.  ...  switch to ATOMIC, and the packets will be serially processed in ingress order automatically.  ... 
doi:10.1109/icpads.2009.109 dblp:conf/icpads/WangQYXL09 fatcat:sxzyawtq35bezb67j3tsvia7fa

Modelling and Simulation of 128-Bit Crossbar Switch for Network On Chip

Mohammad Ayoub Khan, Abdul Quaiyum Ansari
2011 International Journal of VLSI Design & Communication Systems  
The crossbar is a vital component of in any NoC router. In this work, we have designed a crossbar interconnect for serial bit data transfer and 128-parallel bit data transfer.  ...  We have shown comparision between power and delay for the serial bit and parallel bit data transfer through crossbar switch.  ...  ACKNOWLEDGMENT The authors wish to acknowledge the financial support received from University Grants Commission, Ministry of Human Resource Development, Govt. of India, during the course of this project  ... 
doi:10.5121/vlsic.2011.2318 fatcat:lfw3ix34uvd63hm26fstvgtffy

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks

Raymond R. Hoare, Zhu Ding, Shenchih Tung, Rami Melhem, Alex K. Jones
2005 Journal of Parallel and Distributed Computing  
From our network simulation results, we conclude that predictive circuit switching exceeds the performance of packet switching for highly predictable traffic, like collective communications, and for heavily  ...  for performance estimation of the final ASIC implementation.  ...  Four wire delay models (a) parallel to serial, (b) high-speed serial, (c) serial to parallel and (d) parallel wires.  ... 
doi:10.1016/j.jpdc.2005.04.022 fatcat:xmmvvyqq5nddrgacfkfr77mrwe

Low-power network-on-chip for high-performance SoC design

Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure.  ...  An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-onchip (SoC) design.  ...  on a physical level, still staying in a high-level analysis.  ... 
doi:10.1109/tvlsi.2005.863753 fatcat:bkrguqc3tvfzrfz4355asucr7y

Implementation and Performance Enhancement of a PC Based LAN/WAN Router with a Differential QOS Feature [chapter]

S. V. R. Anand, Anurag Kumar
1995 Computer Networks, Architecture and Applications  
The basic router functionality is achieved by integrating a commercially available synchronous serial port card for the PC-AT bus, and our enhancements of public domain or licensed pre-production source  ...  In this paper we describe our approach to, and experiences in, developing a PC based IEEE 802.3 LAN-X.25 WAN IP router.  ...  There are differences between our work and the existing work on QoS control in high speed networks.  ... 
doi:10.1007/978-0-387-34887-2_18 fatcat:qulqr37mafftdkuvjlwr5r2bly

Current Status of Network Processors

Neha Jain, Manoj Kumar Jain
2014 International Journal of Computer Applications  
This paper shows some details about softwares which help in writing code for NPs. Some brief information about NPs is also shown in this paper, which is currently in market.  ...  Number of internet users is increasing day by day. Demands for new application are also increasing. It is possible to create a network processor based on user's demands.  ...  The speed of FP3 network processor is four times faster than the speed of the most advanced networks available today. It provides high performance and advanced Quality of Service (QoS).  ... 
doi:10.5120/17239-7573 fatcat:m224btgssjakxfi5y6qagvasom

Saturating the transceiver bandwidth

Zefu Dai, Jianwen Zhu
2012 Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays - FPGA '12  
This makes it possible to build high bandwidth, high radix switches directly on FPGA that rivals ASIC performance.  ...  In answering this question, we propose a new switch fabric organization, called Grouped Crosspoint Queued switch, that brings significant memory efficiency over the state-ofthe-art organizations.  ...  The authors like to thank Canwen Xiao for his critiques and help in the network simulation.  ... 
doi:10.1145/2145694.2145706 dblp:conf/fpga/DaiZ12 fatcat:6jhpeb2vzvcnbauz5yctvblq64

Internet-Router Buffered Crossbars Based on Networks on Chip

Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
2009 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools  
The scalability and performance of the Internet depends critically on the performance of its packet switches.  ...  We analyzed the performance of our architecture both analytically and by simulation, and show that it performs well for a wide range of traffic conditions and switch sizes.  ...  INTRODUCTION Current high-performance Internet packet switches are based on crossbar fabrics [1] , [2] , and come in two flavours: unbuffered and internally buffered.  ... 
doi:10.1109/dsd.2009.211 dblp:conf/dsd/GoossensMS09 fatcat:kqirvxam75efnnwskszcwbt6ni

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Guruprasad S P, Chandrasekar B.S
2019 International Journal of Advanced Computer Science and Applications  
The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR).  ...  The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch  ...  The protocol converting Gateway works on Most of the OSI layers [5] [6] . The high-performance computation needs high-speed interconnection like Ethernet and Infiniband.  ... 
doi:10.14569/ijacsa.2019.0100937 fatcat:ar7gubydlbeevmkmcth5nvgzki

FIFO based multicast scheduling algorithm for VOQ packet switches

D. Pan, Y. Yang
2004 International Conference on Parallel Processing, 2004. ICPP 2004.  
However, existing queueing based packet switches and scheduling algorithms cannot perform well under multicast traffic.  ...  Many networking/computing applications require high speed switching for multicast traffic at the switch/router level to save network bandwidth.  ...  focus of high speed switches.  ... 
doi:10.1109/icpp.2004.1327938 dblp:conf/icpp/PanY04 fatcat:gr7p4arhynbrpbbp63yomcyoja

Routers with a single stage of buffering

Sundar Iyer, Rui Zhang, Nick McKeown
2002 Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications - SIGCOMM '02  
The model includes architectures in which a switch fabric is sandwiched between two stages of buffering.  ...  Most high performance routers today use combined input and output queueing (CIOQ).  ...  The total memory bandwidth indicates the total bandwidth of the high-speed serial links that connect the memories to control logic.  ... 
doi:10.1145/633025.633050 dblp:conf/sigcomm/IyerZM02 fatcat:oah7e3aegjev5ej66uymljxyj4

Routers with a single stage of buffering

Sundar Iyer, Rui Zhang, Nick McKeown
2002 Proceedings of the 2002 conference on Applications, technologies, architectures, and protocols for computer communications - SIGCOMM '02  
The model includes architectures in which a switch fabric is sandwiched between two stages of buffering.  ...  Most high performance routers today use combined input and output queueing (CIOQ).  ...  The total memory bandwidth indicates the total bandwidth of the high-speed serial links that connect the memories to control logic.  ... 
doi:10.1145/633049.633050 fatcat:co4cpni4qvc3fe4vwg26t2usiu
« Previous Showing results 1 — 15 out of 5,753 results