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A Modeling and exploration framework for interconnect network design in the nanometer era
2009
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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We explore the use of CNTs as both interconnects and vias. Various area, power and performance tradeoffs are explored at the circuit-level to map the RC design space using CNTs. ...
Introduction To provide a well-balanced design in a power and areaconstrained manycore system, and enable performance scaling with increase in number of cores, high-throughput energy-efficient on-chip ...
doi:10.1109/nocs.2009.5071454
dblp:conf/nocs/JoshiCS09
fatcat:qpep4impzjehbak7ivlppfwk4e
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
[chapter]
2004
Lecture Notes in Computer Science
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the on-chip interconnection network. ...
In this paper, we address the problem of high-level exploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. ...
[12] focused on the need to model power and performance in interconnection networks for multiprocessor design, and they proposed a power model of routers and links. ...
doi:10.1007/978-3-540-30205-6_54
fatcat:d7dail7thbdjhcb3b3dajjuteu
Polymorphic On-Chip Networks
2008
2008 International Symposium on Computer Architecture
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We begin this study with an area-performance analysis of the interconnect design space. ...
NoC Designs: To explore a wide range of network on chip (NoC) designs, we vary not only the network parameters, ...
Fellowship, Google Anita Borg Scholarship (Kim), and support from Intel and Dell. ...
doi:10.1109/isca.2008.25
dblp:conf/isca/KimDOA08
fatcat:xucwu54uxvdmtk2u4wu2qvhtje
Polymorphic On-Chip Networks
2008
SIGARCH Computer Architecture News
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We begin this study with an area-performance analysis of the interconnect design space. ...
NoC Designs: To explore a wide range of network on chip (NoC) designs, we vary not only the network parameters, ...
Fellowship, Google Anita Borg Scholarship (Kim), and support from Intel and Dell. ...
doi:10.1145/1394608.1382131
fatcat:wrhq7u66s5hwbb4celwzeizany
Guest Editorial: Special Section on Optical Interconnects and Packaging
1994
Optical Engineering: The Journal of SPIE
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This quantitative analysis is also intended for incorporation later into a computer-aided design system for carrying out signal integrity analysis on optical interconnection links. ...
Koh, Carter, and Boyd present an optical interconnection network design for synchronous global clock distribution on MCMs using a hybrid (silicon oxynitride/ silica glass) H-tree waveguide structure and ...
This quantitative analysis is also intended for incorporation later into a computer-aided design system for carrying out signal integrity analysis on optical interconnection links. ...
doi:10.1117/12.181751
fatcat:jvi5uelikjb2dktfq5ei5nypcm
JADE
2016
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems - AISTECS '16
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JADE simulation features include detailed electrical and optical interconnections, detailed memory hierarchy infrastructure, and built-in energy analysis allowing studies of a broad spectrum of systems ...
Due to its huge design space, evaluating candidate multicore architectures in early design stages, when the number of variables is at its maximum, is challenging. ...
JADE allows early design space exploration, with quick evaluation of the system performance and behavior. ...
doi:10.1145/2857058.2857066
dblp:conf/hipeac/MaedaYWW0WLDW16
fatcat:ogxjh6ztovh2zbsycxt76dnctq
NoCIC
2004
Proceedings of the 2004 international workshop on System level interconnect prediction - SLIP '04
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Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. ...
In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs ...
RIPE [4] , Rensselaer Interconnect Performance Estimator, explores the effect of interconnect design and technology trade-offs on IC performance. ...
doi:10.1145/966747.966762
dblp:conf/slip/VenkatramanLJKZB04
fatcat:62d6q5kqt5btvk7rxhozdmu4za
NoCIC
2004
Proceedings of the 2004 international workshop on System level interconnect prediction - SLIP '04
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Performance and power of on-chip interconnects in the nanometer realm have been an increasing source of concern to designers. ...
In this paper we present a spice-based tool: No-CIC: Network-on-Chip Interconnect Calculator, which enables NoC designers to assess the impact of interconnect circuit designs and understand the tradeoffs ...
RIPE [4] , Rensselaer Interconnect Performance Estimator, explores the effect of interconnect design and technology trade-offs on IC performance. ...
doi:10.1145/966759.966762
fatcat:e5y4tlhxmvgpfkz3adz3qwqffu
Plug-in of power models in the StepNP exploration platform
2004
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '04
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The first goal of our work is to plug-in PIRATE, a parameterizable Network on-Chip in the StepNP platform, to support a fast exploration of on-chip interconnection networks. ...
In this paper, we propose a power/performance estimation layer designed for StepNP, a system-level architecture simulation and exploration platform for Network Processors and Multi-Processor Systems-on-Chip ...
The design space exploration of the communication infrastructure for MP-SoCs requires the definition of a design framework to support the analysis and comparison of different on-chip micro-network architectures ...
doi:10.1145/1023833.1023847
dblp:conf/cases/BeltramePSS04
fatcat:nmblpfydbrchdes36cpdmuitju
Guest Editorial System-Level Interconnect Prediction
2007
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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consumption, delay and yield, required for design space exploration and design optimization. ...
The second NoC paper, "Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors," by Murali et al., focuses on the importance of performance predictability when ...
doi:10.1109/tvlsi.2007.900756
fatcat:cjrhpal5mvhunfsj64rkyiaakm
Guest Editors' Introduction: Silicon Nanophotonics for Future Multicore Architectures
2014
IEEE design & test
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(SNR) and performance in optical on-chip networks. ...
His research interests include embedded, mobile, and high-performance computing, with an emphasis on emerging post-CMOS technologies and design space exploration for energy and reliability in many-core ...
doi:10.1109/mdat.2014.2355512
fatcat:ceocas5jknbkheaakvet2iyzeq
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
2008
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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In this paper, we describe the implementation of an architecture-level early-stage design space exploration tool that incorporates the effect of process and temperature variation for Network-on-chips(NoC ...
and temperature variation during early design exploration. ...
support in Orion and valuable suggestions on this work, Li Shang and Yonghong Yang of Queen's University for their assistance with ISAC thermal simulator, Niraj Jha of Princeton University for insightful ...
doi:10.1109/nocs.2008.4492731
fatcat:a76flhoklfdxbic6p7waqgsal4
Sensitivity evaluation of global resonant H-tree clock distribution networks
2006
Proceedings of the 16th ACM Great Lakes symposium on VLSI - GLSVLSI '06
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The analysis focuses on the effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing ...
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. ...
This paper explores the sensitivity of a resonant H-tree sector to six different design criteria: variations in buffer output resistance, on-chip inductor and capacitor size, and signal and shield line ...
doi:10.1145/1127908.1127955
dblp:conf/glvlsi/RosenfeldF06
fatcat:lje2gmio4jbrviucmz2un5wsu4
Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks
2014
2014 IEEE 22nd Annual Symposium on High-Performance Interconnects
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In this paper, we perform comprehensive design exploration of inter-chip photonic links and networking architectures. ...
of silicon photonic chip-to-chip designs. ...
ACKNOWLEDGEMENTS We gratefully acknowledge support for this work under MIT Lincoln Laboratory PO MIT-7000135026 and the U.S. Department of Energy Sandia National Laboratories PO 1426332. ...
doi:10.1109/hoti.2014.14
dblp:conf/hoti/HendryNRB14
fatcat:n3rgzx5vlzfl7ia54vvctxt7tu
OIL
2009
Proceedings of the 11th international workshop on System level interconnect prediction - SLIP '09
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In this paper, we present OIL, a parameterized Optical Interconnect Library of silicon nano-photonic devices for system level interconnect planning/analysis and low power high performance design exploration ...
under a new holistic photonic Networks-on-Chip architecture. ...
design explorations of on-chip nanophotonic interconnect. ...
doi:10.1145/1572471.1572475
dblp:conf/slip/DingP09
fatcat:qcayeyu3cnevfliwmbcfgnqhuy
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