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Test development for second-generation ColdFire microprocessors

D. Amason, A.L. Crouch, R. Eisele, G. Giles, M. Mateja
1998 IEEE Design & Test of Computers  
The scan vectors used for AC purposes-that is, for timing specification measurements-were generated using the path delay fault model.  ...  Designers proposed the multiplexed D flip-flop scan architecture style because it appeared to impact silicon area the least. Path delay.  ...  Acknowledgments We thank the ColdFire microprocessor design and product engineering teams for their contributions to this work, and we thank Matthew Pressly, specifically, for his participation.  ... 
doi:10.1109/54.706036 fatcat:wxlpxssoobesrdihcngbutjeje

Testability features of the AMD-K6 microprocessor

R.S. Fetherson, I.P. Shak, S.C. Ma
1998 IEEE Design & Test of Computers  
AMD offers the K6 in a range of operating speeds and price points, providing its OEM customers flexibility in configuring personal computer product lines.  ...  However, we had to adapt some cell models for the path delay fault ATPG methodology. For example, a circuit designer may introduce redundancy for performance enhancement or hazard removal.  ...  For path delay fault ATPG, however, we preserved functionally redundant paths because a delay fault may actually cause such a path to fail.  ... 
doi:10.1109/54.706035 fatcat:m622tzx4p5dtzhpin5jnuopjlu

TRUE SYNTHESIZABLE CRITICALPATH AND FALSE PATH FILTERING USING ATPG

Samarshekar ., Ramesh S R
2016 International Journal of Engineering and Technology  
Static Timing Analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions.  ...  This work aims to generate synthesizable critical path and to reduce the number of false paths by using fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults.  ...  The goal for the dynamic analysis is to get a 100% test fault coverage, so that all the paths in the circuit detected.As in this methodology optimised gate-level netlist is generated from Design compiler  ... 
doi:10.21817/ijet/2016/v8i6/160806231 fatcat:wbzilxyn2rcfnds2nl2nuqycbi

RTL analysis and modifications for improving at-speed test

Kai-Hui Chang, Hong-Zu Chou, I. L. Markov
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
To address this challenge, we propose a methodology that identifies robustness problems at the Register Transfer Level (RTL) and fixes them.  ...  However, at-speed fault coverage and test-efficacy suffer when tests are not robust.  ...  Acknowledgment: The authors want to thank Zahi Abuhamdeh (SiliconDFx) for motivating this work.  ... 
doi:10.1109/date.2012.6176504 dblp:conf/date/ChangCM12 fatcat:yr2bgpp7fbe2dadyfjdfz4tg3u

Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

2020 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance.  ...  In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive  ...  support for carrying out this work as part of my PhD work  ... 
doi:10.35940/ijitee.b7841.129219 fatcat:fduob35a3bflfch6eaxfcjl6oa

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E Chen
2007 Journal of electronic testing  
In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes.  ...  A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated.  ...  However, the proposed core test standard is designed for traditional test methodology, and the signal integrity issue is not considered under this framework.  ... 
doi:10.1007/s10836-007-0759-5 fatcat:gcctovsylbcqbfr6hl7khd3oyi

A novel framework for faster-than-at-speed delay test considering IR-drop effects

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
We propose a novel framework for pattern generation/application using any commercial no-timing ATPG tool, to screen small delay defects and a technique to determine the optimal test frequency considering  ...  This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. We present a case study of IR-drop effects due to faster-than-at-speed test.  ...  The PLI provides a standard interface to the internal data representation of the design during simulation.  ... 
doi:10.1145/1233501.1233541 dblp:conf/iccad/AhmedTJ06 fatcat:xdt5qatxdbgy3m36zddgo7igiq

A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
We propose a novel framework for pattern generation/application using any commercial no-timing ATPG tool, to screen small delay defects and a technique to determine the optimal test frequency considering  ...  This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. We present a case study of IR-drop effects due to faster-than-at-speed test.  ...  The PLI provides a standard interface to the internal data representation of the design during simulation.  ... 
doi:10.1109/iccad.2006.320136 fatcat:ha4ozgz7yvhntj5p35nvmyoioa

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2007 Proceedings - Design Automation Conference  
A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools.  ...  The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay.  ...  The design-for-test was implemented hierarchically using full-scan methodology (Synopsys DFT Compiler [22] ) with 16 scan chains inserted and approximately 23K scan cells.  ... 
doi:10.1109/dac.2007.375222 fatcat:lt7w5t5msnd2hk37lhzgjw7qwa

Transition delay fault test pattern generation considering supply voltage noise in a SOC design

Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2007 Proceedings - Design Automation Conference  
A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools.  ...  The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay.  ...  The design-for-test was implemented hierarchically using full-scan methodology (Synopsys DFT Compiler [22] ) with 16 scan chains inserted and approximately 23K scan cells.  ... 
doi:10.1145/1278480.1278616 dblp:conf/dac/AhmedTJ07 fatcat:e746qjmmgvcwdphrco5hh7fsmq

CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework

Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd Austin
2008 2008 IEEE International Conference on Computer Design  
Given a hardware description model of the design under analysis, CrashTest is capable of orchestrating and performing a comprehensive design resiliency analysis by examining how the design reacts to faults  ...  Upon completion, CrashTest provides a high-fidelity analysis report obtained by performing a fault injection campaign at the gate-level netlist of the design.  ...  From that set of flip-flops we choose only those that have a path delay with a timing slack smaller than a predefined threshold specified by the user (i.e.Logic transformation for the path-delay fault  ... 
doi:10.1109/iccd.2008.4751886 dblp:conf/iccd/PellegriniCZSBA08 fatcat:7ukprqsrn5fcxd2odz6ymjk55e

Standard-cell-based design methodology for high-performance support chips

B. Kick, U. Baur, J. Koehl, T. Ludwig, T. Pflueger
1997 IBM Journal of Research and Development  
We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390@ Parallel Enterprise Server Generations 3 and 4.  ...  The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques.  ...  scan design (LSSD) rules [26] .  ... 
doi:10.1147/rd.414.0505 fatcat:55bfzxnupnaxnmff6zhicokls4

Delay defect screening for a 2.16GHz SPARC64 microprocessor

Noriyuki Ito, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi, Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara (+3 others)
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
A nonrobust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targeting a stuck-at fault test.  ...  We estimate the distribution of the delay of paths covered by our delay test.  ...  In the delay test for a standard scan design, the test vector is loaded and the result is unloaded through scan chains.  ... 
doi:10.1145/1118299.1118387 fatcat:5ocglleelngpdhvkwoq65yr7qm

Output Hazard-Free Transition Delay Fault Test Generation

Sreekumar Menon, Adit D. Singh, Vishwani Agrawal
2009 2009 27th IEEE VLSI Test Symposium  
Scan based timing comparison tests offer a potential solution to the problem of small delay detection in aggressive nanometer technologies.  ...  In this paper we present the first systematic ATPG driven approach for generating high coverage output hazard free TDF tests for scan delay testing.  ...  transition delay faults, where v2 is a one-bit scan shift vector for v1.  ... 
doi:10.1109/vts.2009.40 dblp:conf/vts/MenonSA09 fatcat:jdinyc3twbditkgjcdh4cli6ea

High-frequency, at-speed scan testing

Xijiiang Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, N. Tamarapalli
2003 IEEE Design & Test of Computers  
They present techniques for optimizing ATPG across multiple clock domains and propose methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.  ...  At-speed scan testing has demonstrated many successes in industry. One key feature is its ability to use on-chip clock for accurate timing in the application of test vectors in a tester.  ...  Acknowledgments We are grateful for discussions and contributions from Cam L. Lu and Robert B. Benware of LSI Logic regarding efficient merging of transition and stuck-at pattern sets.  ... 
doi:10.1109/mdt.2003.1232252 fatcat:qe5gwnwxjzftldugqyocau5kme
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