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Path Selection Based Acceleration of Conditionals in CGRAs

Shri Hari Rajendran Radhika, Aviral Shrivastava, Mahdi Hamzeh
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015   unpublished
In this paper, we propose a solution in which after resolving the branching condition, we fetch and execute instructions only from the path taken by branch.  ...  Coarse Grain Reconfigurable Arrays (CGRAs) are promising accelerators capable of achieving high performance at low power consumption.  ...  The final result is selected between outputs of two paths based on outcome of the conditional operation (predicate value) as shown in figure 2(d).  ... 
doi:10.7873/date.2015.0788 fatcat:nme3bqu6rfchtlkr7lzbvwf3zm

Branch-aware loop mapping on CGRAs

Mahdi Hamzeh, Aviral Shrivastava, Sarma Vrudhula
2014 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)  
Our experiments show: i) 40% of loops that can be accelerated on CGRA have conditionals, ii) The proposed dual-issue scheme enables our compiler to accelerate loops 40% faster than full predication scheme  ...  In this paper, we develop compiler techniques to map loops with conditionals on CGRA for the dual-issue scheme.  ...  If the same variable is being updated in both the if-part and the else-part, the final result is computed by selecting the output from the path that must have been executed based on the evaluation of the  ... 
doi:10.1109/dac.2014.6881434 fatcat:qkgbdasyojblfl4ybllhcnq6zi

Branch-Aware Loop Mapping on CGRAs

Mahdi Hamzeh, Aviral Shrivastava, Sarma Vrudhula
2014 Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14  
Our experiments show: i) 40% of loops that can be accelerated on CGRA have conditionals, ii) The proposed dual-issue scheme enables our compiler to accelerate loops 40% faster than full predication scheme  ...  In this paper, we develop compiler techniques to map loops with conditionals on CGRA for the dual-issue scheme.  ...  If the same variable is being updated in both the if-part and the else-part, the final result is computed by selecting the output from the path that must have been executed based on the evaluation of the  ... 
doi:10.1145/2593069.2593100 dblp:conf/dac/HamzehSV14 fatcat:rcehydan5rhkbi3zb5ic2qxm6a

Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures

Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi, Luca Benini
2017 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)  
in accelerating either only inner loop bodies, or transformed loops specifically adapted to the target CGRA.  ...  In the approaching era of IoT, flexible and low power accelerators have become essential to meet aggressive energy efficiency targets.  ...  If both the if-part and the else-part update the same variable, the final result is computed by selecting the output from the path that must have been executed based on the evaluation of the branch condition  ... 
doi:10.1109/aspdac.2017.7858308 dblp:conf/aspdac/DasMCRB17 fatcat:3bevwy4dwnafbf2b4epazh4icq

Accelerating Nested Conditionals on CGRA with Tag-based Full Predication Method

Jiang Sha, Wenbo Song, Yu Gong, Yingying Zhao
2020 IEEE Access  
In this paper, a novel tag-based full predication (TFP) strategy is proposed, trying to eliminate redundant operations and thus accelerate NITE on CGRAs.  ...  Tackling with this problem, existing techniques such as partial predication and full predication introduce extra conditional move and select operations, while state-based full predication (SFP) introduces  ...  In order to accelerate the execution of NITE on CGRAs, we propose a novel full predication scheme based on tag scheme.  ... 
doi:10.1109/access.2020.3001220 fatcat:fs6p56g6yjdbvi27vv7oixzefe

An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems

Xiaoyi Ling, Takahiro Notsu, Jason Anderson
2021 2021 24th Euromicro Conference on Digital System Design (DSD)  
CGRAs are promising platforms for the implementation of domain-specific accelerators.  ...  In this thesis, we present a framework for building hybrid processor/accelerator systems to realize compute-kernel acceleration. Each system comprises a RISC-V processor and a CGRA.  ...  Line 22 writes the sentinel value to the end of the a1 array. Line 26 and 29 select data-based control to terminate CGRA.  ... 
doi:10.1109/dsd53832.2021.00015 fatcat:ztixq3bh4jfn7c7qcmmvor4kfy

Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures

Kanishkan Vadivel, Mark Wijtvliet, Roel Jordans, Henk Corporaal
2017 2017 Euromicro Conference on Digital System Design (DSD)  
This paper investigates three hardware based loop optimization techniques that can significantly improve the energy efficiency of CGRAs.  ...  However, CGRAs also have the potential to achieve very high energy efficiency in comparison to other reconfigurable architectures when hardware optimizations are applied.  ...  The inputs and outputs of FUs are connected to switchbox networks to form a reconfigurable data-paths in CGRAs.  ... 
doi:10.1109/dsd.2017.83 dblp:conf/dsd/VadivelWJC17 fatcat:q3yydekqzfdypmybkvfjh6kune

Energy Efficient Acceleration Of Floating Point Applications Onto CGRA

Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy
2020 ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)  
In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications.  ...  Experimental results show that the proposed accelerator achieves a maximum of 4.61× speed-up compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative  ...  Section II discusses the state of the art in the context of floating point acceleration in CGRAs.  ... 
doi:10.1109/icassp40776.2020.9054613 dblp:conf/icassp/DasPMC20 fatcat:lbaxxoa3wvbwhmgi2arfnqqew4

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing

Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
2018 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultra-low power accelerators for near-sensor processing.  ...  The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100MHz, 0.6V in 28nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to  ...  If both the if-part and the else-part update the same variable, the result is computed by selecting the output from the path that must have been executed based on the evaluation of the branch condition  ... 
doi:10.1109/tcad.2018.2834397 fatcat:hf6fekk4ivdkhncpycvpabsswq

UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

Dennis Wolf, Andreas Engel, Tajas Ruschke, Andreas Koch, Christian Hochberger
2021 Journal of Signal Processing Systems  
AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements.  ...  This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail.  ...  Within this environment, the submodules of the control algorithm to be accelerated by the CGRA can be selected.  ... 
doi:10.1007/s11265-021-01641-7 fatcat:b7tv7hn5xjh6bjmhyvoczvpape

Coarse-Grained Reconfigurable Array Architectures [chapter]

Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts
2010 Handbook of Signal Processing Systems  
Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures.  ...  This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs.  ...  This is in fact no different from other multi-core or accelerator-based platforms.  ... 
doi:10.1007/978-1-4419-6345-1_17 fatcat:z6ofpiaaxbffjdfpg5nac4uhbq

BrainWave

Barry de Bruin, Kamlesh Singh, Jos Huisken, Henk Corporaal
2020 Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design  
Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of  ...  in the public portal.  ...  The feature selection is motivated by the feature importance evaluation that is conducted in the work of Wang et al. [1] .  ... 
doi:10.1145/3370748.3406571 dblp:conf/islped/BruinSHC20 fatcat:p2ha5tx5azfu3f3k5aciovx3wm

Coarse-Grained Reconfigurable Array Architectures [chapter]

Bjorn De Sutter, Praveen Raghavan, Andy Lambrechts
2013 Handbook of Signal Processing Systems  
Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures.  ...  This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs.  ...  This is in fact no different from other multi-core or accelerator-based platforms.  ... 
doi:10.1007/978-1-4614-6859-2_18 fatcat:67as5n47rjgy7h2ouudh6pfn3e

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
2020 IEEE Access  
In this paper, we survey the landscape of CGRAs.  ...  Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance  ...  This article is based on results obtained from a project commissioned by New Energy and Industrial Technology Development Organization (NEDO).  ... 
doi:10.1109/access.2020.3012084 fatcat:xx6k4lxbjbc4tjebbymp42w634

CGRA express

Yongjun Park, Hyunchul Park, Scott Mahlke
2009 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems - CASES '09  
In this paper, dynamic operation fusion is introduced to enable CGRAs to effectively accelerate latency-constrained code regions.  ...  In these situations, CGRAs are ineffective as the majority of the resources remain idle.  ...  library in typical operation conditions.  ... 
doi:10.1145/1629395.1629433 dblp:conf/cases/ParkPM09 fatcat:p4durjuuc5b6hoiyq2hfaske6a
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