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Past Time LTL Runtime Verification for Microcontroller Binary Code
[chapter]
2011
Lecture Notes in Computer Science
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This paper presents a method for runtime verification of microcontroller binary code based on past time linear temporal logic (ptLTL). ...
Furthermore, we demonstrate techniques for synthesizing the hardware and software units required to monitor the validity of ptLTL specifications. ...
Past Time LTL While past time operators do no yield extended expressive power of future time LTL [10, Sect. 2.6], a specification including past time operators may sometimes be more natural to a test engineer ...
doi:10.1007/978-3-642-24431-5_5
fatcat:pdmmbanhx5dg7cybtp72ubwlqa
Automated Test-Trace Inspection for Microcontroller Binary Code
[chapter]
2012
Lecture Notes in Computer Science
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This paper presents a non-intrusive framework for runtime verification of executable microcontroller code. ...
The truth verdicts over the assertions are the inputs to a custom-designed µCPU unit that evaluates past-time LTL specifications in parallel to program execution. ...
Runtime Verification for Microcontroller Binary Code This section presents our framework for non-intrusive runtime verification of microcontroller binary code (see Fig. 1 ). ...
doi:10.1007/978-3-642-29860-8_18
fatcat:wynlkvbgifgubkcarssy2upi74
Temporal Monitors for TinyOS
[chapter]
2013
Lecture Notes in Computer Science
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We instrument the original node software to signal asynchronous atomic events to a local nesC component running a runtime verification algorithm; this checks LTL properties automatically translated into ...
In this paper, we report on experimenting with online, node-local temporal monitors for networked embedded nodes running the TinyOS operating system and programmed in the nesC language. ...
None of these tools applies formal methods for runtime verification, and only support temporal properties expressed as small automata by the programmer, or quantitative temporal properties with heavy code ...
doi:10.1007/978-3-642-35632-2_12
fatcat:wxha2dktnjaunnnqnzy4i7c5kq
Runtime verification of embedded real-time systems
2013
Formal methods in system design
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We present a runtime verification framework that allows on-line monitoring of past-time Metric Temporal Logic (ptMTL) specifications in a discrete time setting. ...
For example, for the most general operator considered, the time-bounded Since operator, we obtain a time complexity that is doubly logarithmic both in the point in time the operator is executed and the ...
Past-time linear temporal logic A popular logic in runtime verification is the past-time fragment of LTL (ptLTL), mainly due to: (i) observer generation for ptLTL is straightforward [39, Sect. 5] , and ...
doi:10.1007/s10703-013-0199-z
pmid:26752679
pmcid:PMC4699739
fatcat:rdbxwnp6ejcu7hprmnzt2tctji
Keynote: Hierarchical Fault Detection in Embedded Control Software
2008
2008 32nd Annual IEEE International Computer Software and Applications Conference
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We propose a two-tiered hierarchical approach for detecting faults in embedded control software during their runtime operation: The observed behavior is monitored against the appropriate specifications ...
Note since the control changes only at the discrete times when the system/environment states are sampled, the controlledsystem has a discrete-time hybrid dynamics which can be modeled as an I/O-EFA. ...
A LTL formula is called a past-tense formula if it does not contain any future-tense operators. ...
doi:10.1109/compsac.2008.60
dblp:conf/compsac/ZhouKJ08
fatcat:cup5uk4prbhpjk6hspzdp2iwju
Using Architectural Runtime Verification for Offline Data Analysis
2021
Journal of Automotive Software Engineering
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Architectural Runtime Verification (ARV) is an approach specifically designed for the integrator-a generic way to analyze system behavior on architecture level using the principles of Runtime Verification ...
Instead, it relies on source code debugging or visualizing signals and events. ...
Figure 8 8 Prototype of a graphical frontend for architectural runtime verification (ARV).
Table 2 2 Mapping of the runtime data. ...
doi:10.2991/jase.d.210205.001
fatcat:ulpu4uad2fb2tcxqmunfoggyy4
On the TOCTOU Problem in Remote Attestation
[article]
2021
arXiv
pre-print
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We present two alternative techniques - RATAa and RATAb - suitable for devices with and without real-time clocks, respectively. ...
Compared with current RA architectures - that offer no TOCTOU protection - RATA incurs no extra runtime overhead. In fact, RATA substantially reduces computational costs of RA execution. ...
For example, if Vrf wants to know if remained in a valid state for the past two hours, Vrf chooses 0 as 0 = − 2ℎ. ...
arXiv:2005.03873v2
fatcat:oewjkublwfgzpl4h773d5lu5q4
First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014
2017
International Journal on Software Tools for Technology Transfer (STTT)
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The first international Competition on Runtime Verification (CRV) was held in September 2014, in Toronto, Canada, as a satellite event of the 14th international conference on Runtime Verification (RV'14 ...
The competition organizers would like to warmly thank all participants for their hard work, the members of the runtime verification community who encouraged them to initiate this work, the Laboratoire ...
All the authors acknowledge the support of the ICT COST Action IC1402 Runtime Verification beyond Monitoring (ARVI). ...
doi:10.1007/s10009-017-0454-5
fatcat:u6hmnzu5tbedtcw7hpjodrgzom
A Survey of Challenges for Runtime Verification from Advanced Application Domains (Beyond Software)
[article]
2018
arXiv
pre-print
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Typically, the two main activities in runtime verification efforts are the process of creating monitors from specifications, and the algorithms for the evaluation of traces against the generated monitors ...
In this paper we present a collection of challenges for runtime verification extracted from concrete application domains, focusing on the difficulties that must be overcome to tackle these specific challenges ...
Acknowledgements This research has been supported by the European ICT COST Action IC1402 (Runtime Verification beyond Monitoring (ARVI)). ...
arXiv:1811.06740v1
fatcat:4bxx5tvfpzez3jidsj22flibv4
A survey of challenges for runtime verification from advanced application domains (beyond software)
2019
Formal methods in system design
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Typically, the two main activities in runtime verification efforts are the process of creating monitors from specifications, and the algorithms for the evaluation of traces against the generated monitors ...
In this paper we present a collection of challenges for runtime verification extracted from concrete application domains, focusing on the difficulties that must be overcome to tackle these specific challenges ...
This research has been supported by the European ICT COST Action IC1402 Runtime Verification beyond Monitoring (ARVI). ...
doi:10.1007/s10703-019-00337-w
fatcat:6vu5odqyjjbkvf255bsxcchane
A multi-paradigm language for reactive synthesis
2016
Electronic Proceedings in Theoretical Computer Science
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The declarative part is expressed in the LTL fragment of generalized reactivity(1), which admits efficient synthesis algorithms, extended with past LTL. ...
These notions are necessary for input to game solvers. The integration of imperative and declarative paradigms allows using the paradigm that is most appropriate for expressing each requirement. ...
Acknowledgments The authors would like to thank Scott Livingston for providing helpful feedback. ...
doi:10.4204/eptcs.202.6
fatcat:sdmkkfjmknb4dlcm2s66fddddu
Modelling and Verification of Large-Scale Sensor Network Infrastructures
2018
2018 23rd International Conference on Engineering of Complex Computer Systems (ICECCS)
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We define a modelling and verification framework based on Bigraphical Reactive Systems (BRS) for modelling, with bigraph patterns and temporal logic properties for specifying application requirements. ...
Performance results for verification of two application properties running on a WSN with up to 200 nodes indicate our framework is capable of handling WSNs of that scale. ...
We also thank Greg Jackson for providing the dataset collected from the microclimate WSN deployment in the Queen Elizabeth Olympic Park. ...
doi:10.1109/iceccs2018.2018.00016
dblp:conf/iceccs/SevegnaniKCM18
fatcat:dzm6ct2c5nfmxpvl2a53poccyi
Kalpa Publications in Computing R2U2: Tool Overview *
unpublished
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R2U2 (Realizable, Responsive, Unobtrusive Unit) is an extensible framework for runtime System Health Management (SHM) of cyber-physical systems. ...
An R2U2 requirement is specified utilizing a hierarchical combination of building blocks: temporal formula runtime observers (in LTL or MTL), Bayesian networks, sensor filters, and Boolean testers. ...
designating how specific code blocks should behave, or by translating design-time architecture specifications in LTL to automata-based runtime monitors. ...
fatcat:62llmwjsife7pj3wputmosxmwy
A two-stage heuristic for the university course timetabling problem
[chapter]
2019
StuCoSReC. Proceedings of the 2019 6th Student Computer Science Research Conference
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Linear Temporal Logic (LTL) is a formalism originally developed for the formal design and verification of computer programs. ...
The parameters are defined using a domain-specific language at compile-time but can change in the runtime with configuration stored in the microcontroller flash for each scenario. ...
Psevdokoda algoritma BA je prikazana v algoritmu 1. for i = 1 to D do 5: if rand(0,1) < CR or n == D then 6: yn = xr1,n + F * (xr2,n + xr3,n); 7: n = (n + 1)%(D + 1); 8: end if 9: end for 10: end if 2.3 ...
doi:10.26493/978-961-7055-82-5.27-30
fatcat:mv36atnxqvczjg7m7aetrpvy6y
OASIcs, Volume 16, MEMICS'10, Complete Volume
[article]
2012
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We would also like to thank the anonymous reviewers for their valuable comments.
Acknowledgements ...
question of deriving test cases from microcontroller binary code. ...
Specification Language In the past, we have carried out a case study [18] in cooperation with an industry partner using [mc]square [21], which is a binary code verification tool. ...
doi:10.4230/oasics.memics.2010
fatcat:hufnlt7gu5b4nocfjdcbkhylcy
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