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Reducing Write Latency by Integrating Advanced PreSET Technique and Two-Stage-Write with Inversion Schemes

Sa'ed Abed
2020 Journal of Computers  
need to be written into the PCM when a write operation is issued.  ...  This is achieved by pre-setting (set to 1) the dirty cache line beforehand and if the process fails, it shifts to Two-Stage-Write with inversion.  ...  The main idea of the new scheme naming it as Partial-PreSET, is to SET the dirty bits of a cache line in a fine-grained fashion other than the previous PreSET which is conducted at a coarse-grained level  ... 
doi:10.17706/jcp.15.1.22-36 fatcat:s2o6ngykpbfidli3y3bbtswmlq