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Computer-aided design of analog and mixed-signal integrated circuits

G.G.E. Gielen, R.A. Rutenbar
2000 Proceedings of the IEEE  
This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs).  ...  need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits.  ...  In addition, analog circuits are more sensitive to nonidealities and all kinds of higher order effects and parasitic disturbances (crosstalk, substrate noise, supply noise, etc.).  ... 
doi:10.1109/5.899053 fatcat:2kjzezalevhuzayfrkykyvm5py

A tutorial introduction to research on analog and mixed-signal circuit testing

L.S. Milor
1998 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.  ...  Traditionally, work on analog testing has focused on diagnosing faults in board designs.  ...  Kao, and the four reviewers for their helpful comments on this manuscript.  ... 
doi:10.1109/82.728852 fatcat:vfon3dk5cvhddpfutzx5dajsau

ComputerAided Design of Analog and MixedSignal Integrated Circuits [chapter]

2009 Computer-Aided Design of Analog Integrated Circuits and Systems  
This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs).  ...  need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits.  ...  In addition, analog circuits are more sensitive to nonidealities and all kinds of higher order effects and parasitic disturbances (crosstalk, substrate noise, supply noise, etc.).  ... 
doi:10.1109/9780470544310.ch1 fatcat:nz4on5owvvdxbneeuh3aqrkkfe

Metrology for analog module testing using analog testability bus

Chanchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
Proceedings of International Conference on Computer Aided Design  
In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic eects in an analog testability bus test environment.  ...  For the test response analysis, we derive an extraction methodology to remove the parasitic eects and obtain the intrinsic response of the CUT.  ...  The rst one is the generation of quality test waveform in an analog testability bus test environment. The second one is the modeling and the measurement of the parasitic effects of analog buses.  ... 
doi:10.1109/iccad.1996.569916 dblp:conf/iccad/SuCJT96 fatcat:jac5ilvb2bgm5jvw5b2nz3st5y