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Parameter Invariant Monitoring for Signal Temporal Logic
2018
Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week) - HSCC '18
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Signal Temporal Logic (STL) is a prominent specification formalism for real-time systems, and monitoring these specifications, specially when (for different reasons such as learning) behavior of systems ...
ABSTRACT Signal Temporal Logic (STL) is a prominent specification formalism for real-time systems, and monitoring these specifications, specially when (for different reasons such as learning) behavior ...
This work was supported in part by NSF CNS-1505799 and the Intel-NSF Partnership for Cyber-Physical Systems Security and Privacy and by ONR N000141712012. ...
doi:10.1145/3178126.3178140
dblp:conf/hybrid/RoohiKWSL18
fatcat:rizvqyb7sfekvosvmxvv5wxe4a
In-circuit temporal monitors for runtime verification of reconfigurable designs
2015
Proceedings of the 52nd Annual Design Automation Conference on - DAC '15
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We present designs for in-circuit monitoring of custom hardware designs implemented in reconfigurable hardware. The monitors check hardware designs against temporal logic specifications. ...
monitor. ...
Temporal logic monitors for software and hardware: Several researchers implement temporal logic monitors. ...
doi:10.1145/2744769.2744856
dblp:conf/dac/TodmanSL15
fatcat:wf5cjj37k5e6hc4ioqa6vch2iq
The HARMONIA Project: Hardware Monitoring for Automotive Systems-of-Systems
[chapter]
2016
Lecture Notes in Computer Science
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The verification of complex mixed-signal integrated circuit products in the automotive industry accounts for around 60 %-70 % of the total development time. ...
Observers embedded on FPGA hardware will be generated from assertions, and used for monitoring automotive designs emulated on hardware. ...
Ezio Bartocci and Dejan Ničković acknowledge also the support of the EU ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI). ...
doi:10.1007/978-3-319-47169-3_28
fatcat:fwwhfmjp3nhljbl5rn2udf2nuy
Algorithms for Reliable Estimation, Identification and Control
2022
Algorithms
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as well as the state and parameter estimation for systems with uncertainty [...] ...
The two-part Special Issue "Algorithms for Reliable Estimation, Identification and Control" deals with the optimization of feedforward and feedback controllers with respect to predefined performance criteria ...
Kröger in their paper A Truly Robust Signal Temporal Logic: Monitoring Safety Properties of Interacting Cyber-Physical Systems under Uncertain Observation [14] , is a linear-time temporal logic designed ...
doi:10.3390/a15080276
fatcat:eqfsbflk7zh2zhy4u5zq7zhh5e
AMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic
[chapter]
2018
Lecture Notes in Computer Science
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The evaluation of the signals is based on rich temporal specifications expressed in extended Signal Temporal Logic (xSTL), which combines Signal Temporal Logic (STL) with Timed Regular Expressions (TRE ...
The tool features qualitative monitoring (property satisfaction checking), trace diagnostics for explaining and justifying property violations and specification-driven measurement of quantitative features ...
Extended Signal Temporal Logic Extended Signal Temporal Logix (xSTL) essentially combines STL with a variant of TRE. ...
doi:10.1007/978-3-319-89963-3_18
fatcat:cokvtqy2ezgyrcv64iv3xcbt6a
A Logic for Monitoring Dynamic Networks of Spatially-distributed Cyber-Physical Systems
[article]
2022
arXiv
pre-print
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2021 pre-print arXiv:2105.11400v2 fatcat:dmqin6elvbhetlfmiihpgsmaeiOther Versions
STREL combines the Signal Temporal Logic with two spatial modalities reach and escape that operate over the weighted graph. ...
We revisit here the Spatio-Temporal Reach and Escape Logic (STREL), a logic-based formal language designed to express and monitor spatio-temporal requirements over the execution of mobile and spatially ...
Examples include Spatial-Temporal Logic (SpaTeL) [HJK + 15], Signal Spatio-Temporal Logic (SSTL) [NBC + 15], Spatial Aggregation Signal Temporal Logic (SaSTL) [MBL + 20, MBL + 21] and Spatio-Temporal Reach ...
arXiv:2105.11400v4
fatcat:drm3vkpabreklplhyfshiv3xjm
Specification-Based Monitoring of Cyber-Physical Systems: A Survey on Theory, Tools and Applications
[chapter]
2018
Lecture Notes in Computer Science
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In the context of discrete systems, software or digital hardware, formalisms such as temporal logic or regular expressions are commonly used. ...
In this chapter, we summarise the state-of-the-art techniques for qualitative and quantitative monitoring of CPS behaviours. ...
Ničković acknowledge the partial support of the EU ICT COST Action IC1402 on Runtime Verification beyond Monitoring (ARVI) and of the HARMONIA (845631) project, funded by a national Austrian grant from ...
doi:10.1007/978-3-319-75632-5_5
fatcat:2m52qvfax5cn3fgyhcl3piy2ui
Monitoring mobile and spatially distributed cyber-physical systems
2017
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design - MEMOCODE '17
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2019 pre-print arXiv:1904.08847v1 fatcat:fazohahnfbhstot5vjqep5qcou
Our logic extends the Signal Temporal Logic with two novel spatial operators reach and escape from which is possible to derive other spatial modalities such as everywhere, somewhere and surround. ...
In this work, we pursue a complementary approach by introducing STREL a novel spatio-temporal logic that enables the specification of spatio-temporal requirements and their monitoring over the execution ...
SPATIO-TEMPORAL REACH AND ESCAPE LOGIC In this section, we present the Spatio-Temporal Reach and Escape Logic (STREL), an extension of the Signal Temporal Logic. ...
doi:10.1145/3127041.3127050
dblp:conf/memocode/BartocciBLN17
fatcat:rifwgo3t3jcwbjkqu4smwsjv3a
Verification of analog and mixed signal designs using online monitoring
2009
2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop
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In this paper, we present a methodology for the specification and verification of AMS designs using online monitoring at runtime based on the notion of System of Recurrence Equations (SREs). ...
Analog and mixed signal (AMS) circuits play an important role in today's System on Chip design. ...
For example in the current implementation, the PSL expression cannot be automatically translated into C language and input to the simulator, which is the subject of our future work. ...
doi:10.1109/ims3tw.2009.5158695
fatcat:nfmrvlzds5gb5m3gfd54g5fkh4
On Temporal Logic and Signal Processing
[chapter]
2012
Lecture Notes in Computer Science
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We present Time-Frequency Logic (TFL), a new specification formalism for real-valued signals that combines temporal logic properties in the time domain with frequency-domain properties. ...
Like hybrid automata and their analysis techniques, the TFL formalism is a contribution to a unified systems theory for hybrid systems. ...
Signal Temporal Logic We present STL in a manner that makes it closer to the world of Control and Signal Processing. ...
doi:10.1007/978-3-642-33386-6_9
fatcat:zf3x3il5orhb3pvfu45wg4bxh4
Anomaly detection in cyber-physical systems: A formal methods approach
2014
53rd IEEE Conference on Decision and Control
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Our procedure constructs from data a signal temporal logic (STL) formula that describes normal system behavior. Trajectories that do not satisfy the learned formula are flagged as anomalous. ...
STL formulae can also be used for early detection via online monitoring and for anomaly mitigation via formal synthesis. ...
Signal temporal logic (STL) [11] is a predicate temporal logic defined over signals. ...
doi:10.1109/cdc.2014.7039487
dblp:conf/cdc/JonesKB14
fatcat:wznbyypxefatpcry62pr7h2gy4
Efficient Parametric Identification for STL
2018
Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week) - HSCC '18
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We describe a new algorithm for the parametric identification problem for signal temporal logic (STL), stated as follows. ...
Given a densetime real-valued signal w and a parameterized temporal logic formula φ, compute the subset of the parameter space that renders the formula satisfied by the signal. ...
PARAMETRIC SIGNAL TEMPORAL LOGIC Parametric Signal Temporal Logic (PSTL) [6] extends the logic STL [33] with parameters. ...
doi:10.1145/3178126.3178132
dblp:conf/hybrid/BakhirkinFM18
fatcat:nsngkym46nboxfq4fena6ry5su
Specification Formalisms for Modern Cyber-Physical Systems (Dagstuhl Seminar 19071)
2019
Dagstuhl Reports
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This report documents the program and the outcomes of Dagstuhl Seminar 19071 "Specification Formalisms for Modern Cyber-Physical Systems." ...
Parameter Invariant Monitoring: Here, the problem is to monitor specifications that may be parametric. ...
Applications include diabetes monitoring.
Spatio-temporal Logic A key question is how to combine spatial and temporal operators? One approach is to consider a signal as a spatio-temporal signal. ...
doi:10.4230/dagrep.9.2.48
dblp:journals/dagstuhl-reports/DeshmukhMN19
fatcat:qs52xpqxbzh6vajciydqb3ujgi
Temporal logic inference for classification and prediction from data
2014
Proceedings of the 17th international conference on Hybrid systems: computation and control - HSCC '14
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We introduce reactive parameter signal temporal logic (rPSTL), a fragment of parameter signal temporal logic (PSTL) that is expressive enough to capture causal, spatial, and temporal relationships in data ...
A temporal logic formula that can discriminate between the desirable behaviors and the undesirable ones is constructed. The formulae also indicate possible causes for each set of behaviors (e.g. ...
The authors would like to acknowledge members of CIDAR group at Boston University for providing experimental data for the gene network presented in [10] . ...
doi:10.1145/2562059.2562146
dblp:conf/hybrid/KongJAGB14
fatcat:ew5nc4yf5bhmpfq3xvqklaf544
Analyzing Mode Confusion via Model Checking
[chapter]
1999
Lecture Notes in Computer Science
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T oday's complex avionics systems make it di cult for pilots to maintain awareness of the actual states, or modes, of the ight deck automation. ...
present paper investigates whether state-exploration techniques, e.g., model checking, are better able to achieve this task than theorem proving and also to compare the verication tools Mur , SMV, and Spin for ...
We thank Ricky Butler and Steve Miller for many enlightening discussions about mode confusion, as well as Ben Di Vito and the anonymous referees for their valuable comments and suggestions. ...
doi:10.1007/3-540-48234-2_9
fatcat:xdwbg2cd2nhgnbojoymlzebkna
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