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In via-switch FPGAs (VS-FPGAs), the via-switches required for reconfiguration are placed in the routing layer so that the entire transistor layer can be utilized for computing, and higher implementation ... These features enable operation with high energy efficiency. This article reports 65 nm prototype fabrication results and predicted the performance of the VS-FPGA designed for AI applications. ... The authors thank all the contributors including students, researchers and engineers who are involved in this project. ...doi:10.35848/1347-4065/ac6b81 fatcat:rbhsxhumdrekvczvuol2ekniui
Chapter II then identifies the computational effects of applying resolution to logic programs and also mentions some common built-in facilities. ... Chapters V and VI comprise the most important part of this text since they introduce an aspect rarely found in other books on logic programming, namely, program verification and synthesis. ...
 on of an Abstract PROLOG Machine An Abstraction in Logic Programming Modularization and Abstraction in Logic Programming Modularization and Abstraction in PROLOG/KR Data Acceptability ... Model to Efficient Compilation of Patterns From Abstract PROLOG Instruction Set An Abstract PROLOG Machine-a Specification  Abstract PROLOG Machine and its Application to Partial Evaluation ... , and Future-(509]Logic Programming- Patterns in Logic Programs Enumeration of Success Patterns From Abstract Model to Efficient Compilation of Performance Measurement of Parallel Logic Program ...doi:10.1016/0743-1066(84)90025-6 fatcat:ypq2jrr3mvd3hflnp6ftrcd5vm
Although much work has been done in parallelization of logic programming more than a decade ago (e.g., Aurora, Muse, YapOR), the current state of parallelizing logic programs is still very poor. ... This work presents a way for parallelism of tabled logic programs in XSB Prolog under the well founded semantics. ... Conclusions and Future Work We presented a novel approach that transforms logic programs under the well founded semantics into parallelized versions and has been implemented in the increval package of ...arXiv:0912.3510v2 fatcat:vqorddu7vrfrdgebcuifhjx7ci
Parallel programs present a variety of challenges including race conditions, synchronization and load balancing overhead. Social media, enterprise mobility, data analytics and cloud. ... Profits and the efficient market. Software development life cycle. Economic – 100 Trillion market value. Tiered industry. Fourth industrial revolution. ... • Parallel programs present a variety of challenges including race conditions, synchronization and load balancing overhead • Social media, enterprise mobility, data analytics and cloud • AI, Technology ...doi:10.6084/m9.figshare.7857710 fatcat:4ztmj4iypzcq7itl7plw2zre4a
. • Goal: assist programmer in arranging parallelism so the data layout and distribution best exploit memory arrangements. Kernel Lattice Parallelism • KeLP: Kernel Lattice Parallelism. ... Programming Model • Programs begin with a single (logical) control thread. • for_all loop iterations: each one executes independently on one SPMD process. • Storage model: distribute each block of data ... very favorably compared to MPI. • Inspector/executor paradigm (MotionPlans vs Movers) allows retargetting to various situations. ...doi:10.1006/jpdc.1998.1437 fatcat:nghso34ejzaybaps6cnj7i3ocq
The research presented herein is geared towards providing additional performance to logic programs through the use of parallelism, while preserving the conventional semantics of logic languages. ... Compilation techniques such as those portrayed by the Warren Abstract Machine (WAM) have greatly improved the speed of execution of logic programs. ... Efficient Parallel Execution of Logic Programs Logic Programs offer many different sources of parallelism  . Ideally, all these sources should be exploited simultaneously in a given system. ...doi:10.1145/25372.25377 fatcat:3ol4sv2g5ncjbfepr6klr2gx5m
Using dylaamic predicate in an or-parallel prolog system. 23. A declarative alternative to "assert" in logic programming. 24. Semantics of logic programs with aggregates. XII. Constraints, I. 25. ... Program transformation and synthesis. 38. Derivation of efficient logic programs by synthesing new predicates. 39. Program tranformation under the principle of proof as program. 40. ...doi:10.1016/0898-1221(92)90096-z fatcat:4pjyhq2h5zcxzcjs7pzcgpop54
Reddy, A typed founda- tion for directional logic programming (282-318); Keehang Kwon, Gopalan Nadathur and Debra Sue Wilson, Implementing a notion of modules in the logic programming language AProlog ... Miller], The z-calculus as a theory in linear logic: preliminary results (242-264); Seppo Keronen, Natural deduction proof theory for logic programming (265-281); Uday S. ...
2011 11th IEEE International Conference on Nanotechnology
critical path for a (511;9) parallel counter implemented in this fabric vs. spin-wave only. ... In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in ... However, since SPWFs enable efficient realization of high fan-in logic, higher order counters can be efficiently implemented using SPWFs. ...doi:10.1109/nano.2011.6144452 fatcat:pyovivytbff6tfqfrjohwlhgiq
By taking advantage of the synergy between logic variables, unification with occurs check and efficient backtracking in today's Prolog systems, we climb 4 orders of magnitude above previously known counts ... Keywords: logic programming transformations, type inference, combinatorics of lambda terms, simply-typed lambda calculus, simply-typed normal forms. ... We thank the anonymous reviewers of LOPSTR'16 for their constructive suggestions and the participants of the 9th Workshop Computational Logic and Applications (https://cla.tcs.uj.edu.pl/) for enlightening ...arXiv:1608.03912v1 fatcat:bxppoupkzzcljlpi3f724o37m4
The suggested algorithm exploits the idea of mixing both logical and physical permutations together. In the logical permutation, the address map is transposed for each data unit access. ... This paper proposes an efficient in-place N-dimensional permutation algorithm. The algorithm is based on a novel 3D transpose algorithm that was published recently. ... of parallel kernels vs. serial kernels. ...doi:10.1016/j.aej.2015.03.024 fatcat:ewxoord4grb6hhzag72guihhqe
Circuits and Systems
The static ALU arrays process instructions in parallel without registers and improve energy efficiency. ... Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) ... Figure 9 . 9 ALU utilization and instruction-level parallelism. Figure 11 . 11 Mico32 vs. DYNaSTA: logic power consumption (fibonacci). ...doi:10.4236/cs.2017.85009 fatcat:o5a7u5fcbjajzlpowf45kmxpf4
In this work we propose a novel HW/SW approach to design energy-efficient ultralow-power systems which combine the key ideas of approximate computing and hybrid memory systems featuring both SCM and 6T-SRAM ... We introduce a novel hardware support to split errortolerant data so to host most significant bits (MSB) in the SCM and least significant bits (LSB) in the 6T-SRAM. ... To fully exploit the parallel capabilities of our multicore platform with a limited programming effort, we adhere to the OpenMP specification  , which provides a model for parallel programming that ...doi:10.1109/tcad.2016.2633474 fatcat:drbmba5xvbfubh2bdtrawwcnre
Lecture Notes in Computer Science
Additionally, a relatively high 1 st level cache miss rate of 7-8% and a lack of memory bandwidth prevent logical processors with hyperthreading technology enabled from achieving further improvement. ... We developed a multithreaded parallel implementation of a sequence alignment algorithm that is able to align whole genomes with reliable output and reasonable cost. ... Execution resources might be shared efficiently between logical processors running independent threads. ...doi:10.1007/978-3-540-39707-6_40 fatcat:vewkmq323jgmlmjt4ha472xsra
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