Filters








1,112 Hits in 3.7 sec

Parallel algorithms for inductance extraction of VLSI circuits

H. Mahawar, V. Sarin
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
This work presents an overview of a new parallel software package for inductance extraction of large VLSI circuits.  ...  Inductance extraction involves estimating the mutual in ductance in a VLSI circuit.  ...  Conclusion This paper presents a high performance parallel software package for inductance extraction of VLSI circuits.  ... 
doi:10.1109/ipdps.2006.1639316 dblp:conf/ipps/MahawarS06 fatcat:uczqecfrzzdxrpwmcaazbosyqq

Fast inductance extraction of large VLSI circuits

H. Mahawar, V. Sarin, Weiping Shi
2002 Proceedings 16th International Parallel and Distributed Processing Symposium  
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits.  ...  Inductance extraction involves the solution of large, dense, complex linear systems of equations by preconditioned iterative methods.  ...  There is significant interest in developing fast, parallel algorithms for inductance extraction of large VLSI circuits.  ... 
doi:10.1109/ipdps.2002.1015524 dblp:conf/ipps/MahawarSS02 fatcat:o7kgsmjzgjbkfiwjherdfhugbq

Parallel software for inductance extraction

H. Mahawar, V. Sarin
2004 International Conference on Parallel Processing, 2004. ICPP 2004.  
This paper describes a parallel software package for inductance extraction called ParIS, which is capable of analyzing interconnect configurations involving several conductors within reasonable time.  ...  The next generation VLSI circuits will be designed with millions of densely packed interconnect segments on a single chip.  ...  Conclusion This paper presents a high performance parallel software package called ParIS for inductance extraction of VLSI circuits.  ... 
doi:10.1109/icpp.2004.1327946 dblp:conf/icpp/MahawarS04 fatcat:voieb6qk3jc7vi4ln52qchry4i

Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms

Wei Wu, Fang Gong, Rahul Krishnan, Hao Yu, Lei He
2013 IEEE design & test  
As a result, the algorithms for circuit simulation cannot be effectively parallelized by simply unfolding "for" loops into parallel code.  ...  However, circuit simulation algorithms for designs at the extreme scale beyond 22 nm and 60 GHz are difficult for parallelization.  ...  In the example of inductance extraction, VNA and matrix stretching are proposed to formulate a BBD matrix for inductive interconnect, and stochastic FMM is developed for capacitance extraction with variation  ... 
doi:10.1109/mdt.2012.2226201 fatcat:ff5h4qyj45cinbloyhupsnf3ua

An efficient algorithm for 3-D reluctance extraction considering high frequency effect

Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
As shown in literatures, partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, because the partial reluctance exhibits much better locality than partial inductance  ...  In this paper, a new reluctance extraction algorithm is proposed considering the high frequency effect.  ...  Introduction The industry of modern VLSI circuits is advancing toward ultra deep sub-micron technology or even nano technology, and the operating frequency of circuit has reached multiple giga-hertz (GHz  ... 
doi:10.1145/1118299.1118425 fatcat:lcg6pcfva5hrdijc7w7xy5itoi

1983 Index IEEE Transactions on Computers Vol. C-32

1983 IEEE transactions on computers  
Addition; Asynchronous sequential logic circuits; Flip- flops; Logic arrays; Multivalued logic circuits; Sequential logic circuits Logic design inductive assertion method for design verification at  ...  ., T-CAug 83 756-760 computing power of VLSI circuits; combinatorial limit. Vuillemin, Jean, T-CMar 83 294-300 designs for VLSI circuits that compute N-element Fourier transforms.  ... 
doi:10.1109/tc.1983.1676190 fatcat:xsogjoynp5dt7mqu6dy4tiodfq

Parallel iterative methods for dense linear systems in inductance extraction

Hemant Mahawar, Vivek Sarin
2003 Parallel Computing  
This paper presents a class of parallel iterative methods for solving the linear systems of equations that arise in the inductance extraction process.  ...  Accurate estimation of the inductive coupling between interconnect segments of a VLSI circuit is critical to the design of high-end microprocessors.  ...  This paper presents a class of parallel algorithms for solving the linear systems of equations that arise in inductance extraction of VLSI circuits.  ... 
doi:10.1016/s0167-8191(03)00100-5 fatcat:vyeebwnfdfdhnjwzoekuzvrnea

An efficient 3D reluctance extractor for on-chip interconnects

Shan Zeng, Wenjian Yu, Xianlong Hong, Zeyi Wang
2006 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings  
1 Partial reluctance based circuit analysis is efficient in capturing on-chip inductance effect, for its better locality than the partial inductance.  ...  In this paper, a new reluctance extraction algorithm is presented considering the high frequency effect.  ...  Introduction The industry of VLSI circuits is advancing toward nanotechnology and the operating frequency of circuits has reached multiple giga-hertz (GHz).  ... 
doi:10.1109/icsict.2006.306251 fatcat:c2atzkixbbfodogexkv5mij4aq

Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits [chapter]

Davood Fathi, Behjat Forouzandeh
2010 Carbon Nanotubes  
Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects.  ...  Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed.  ...  reliability [4] , hence it has a significant impact on the performance and reliability of VLSI circuits.  ... 
doi:10.5772/39430 fatcat:hcljabun2jf53eammjxygzmk4y

Efficient power network analysis with complete inductive modeling

Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng
2009 2009 10th International Symposium on Quality of Electronic Design  
The frequency-domain circuit equation including partial reluctances is derived, and then solved with the GMRES algorithm with rescaling and precondition techniques.  ...  Numerical results show that the proposed method is orders of magnitude faster than HSPICE, and capable of handling the inductive P/G structures with more than 100,000 wire segments.  ...  Modeling the inductive effect of on-chip and off-chip interconnects is another research focus for current nano-scale VLSI chip.  ... 
doi:10.1109/isqed.2009.4810390 dblp:conf/isqed/ZengYZWHC09 fatcat:hrxbgrjgbnf3flxuxncayyx5wi

SASIMI

Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
We present a technique for the fast and accurate simulation of largescale VLSI interconnects with nonlinear devices, called SASIMI.  ...  Numerical results show that SASIMI is up to 1400 times as fast as commercial-grade SPICE, for moderatesize circuits, with little sacrifice in simulation accuracy.  ...  Figure 1 depicts the sparsity structure of the A matrix for a circuit example of parallel wires driving a bank of inverters.  ... 
doi:10.1145/1118299.1118402 fatcat:4md5exsgynanthka2a7imt4qce

Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk

Y. Massoud, J. White
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Kamon for his help modifying the FastHenry program  ...  His research interests include serial and parallel numerical algorithms for problems in circuit, interconnect, device, and micro-electro-mechanical system design. Dr.  ...  REDUCING COUPLING INDUCTANCE SIMULATION RESULTS In order to verify this method of reducing coupling inductance and show its effect on circuit crosstalk, an example of eight parallel 1000 data lines is  ... 
doi:10.1109/tvlsi.2002.1043331 fatcat:elbizfgxazf4rih5nghtbjxvf4

Analysis, reduction and avoidance of crosstalk on VLSI chips

Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl
1998 Proceedings of the 1998 international symposium on Physical design - ISPD '98  
The crosstalk analysis and the routing tool described in this paper were used in three generations of VLSI processor chip designs for IBM's S/390 computers, always resulting in crosstalk-resistant hardware  ...  The method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations.  ...  Acknowledgements We would like to thank the department members of the "VLSI Design Center" of the IBM Development Laboratory in Böblingen for their hints and support for the wording and the contents of  ... 
doi:10.1145/274535.274566 dblp:conf/ispd/StohrAHK98 fatcat:ixssi6haujc5rm57vjavuixqfq

Modeling and extraction of interconnect capacitances for multilayer VLSI circuits

N.D. Arora, K.V. Raol, R. Schumann, L.M. Richardson
1996 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The method extraction of the complete circuit level capacitances at each node in the circuit.  ...  We report an accurate and practical method of estimating interconnect capacitances for a given circuit layout.  ...  in a VLSI circuit.  ... 
doi:10.1109/43.486272 fatcat:4qyfxjtdinazbdfmq7hjf5rj24

2009 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 28

2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
., +, TCAD Nov. 2009 1654-1665 Electromagnetic induction Inductance Extraction for Interconnects in the Presence of Nonlinear Mag- netic Materials.  ...  ., +, TCAD Jan. 2009 46-59 M Magnetic materials Inductance Extraction for Interconnects in the Presence of Nonlinear Mag- netic Materials.  ... 
doi:10.1109/tcad.2009.2036802 fatcat:hxyu2mmrnzfnbi6qlt6bklkgku
« Previous Showing results 1 — 15 out of 1,112 results