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Power optimised hybrid sorting-based median filtering

N. Sambamurthy, M. Kamaraju
2020 International Journal of Digital Signals and Smart Systems  
Nowadays, embedded video and image processing capabilities are much more demands with image quality. Digital image noise mostly occurs in a communication channel.  ...  For this, the filter is designed with hybrid sorting network with intelligent clock gating technique is also presented. The implementation of median filter on ARTIX-7 (90 nm) FPGA.  ...  Pei (2010) suggested VLSI architecture design of simple edge preserved denoising method for reducing impulse noise.  ... 
doi:10.1504/ijdsss.2020.106075 fatcat:43jekgrvsvbxtokaovrw32lolu

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Sergio Saponara, Luca Fanucci, Pierangelo Terreni
2004 EURASIP Journal on Advances in Signal Processing  
A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper.  ...  The VLSI macrocell has been realized in a 0.18 µm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second) 4CIF, with a  ...  We would like to thank the anonymous reviewers for useful comments and suggestions.  ... 
doi:10.1155/s1110865704403035 fatcat:a65slhogqnadjojfwkzh37v4py

Journal of Real-Time Image Processing: third issue of volume 11

Matthias F. Carlsohn, Nasser Kehtarnavaz
2016 Journal of Real-Time Image Processing  
The third paper by Guler et al. presents ''Real-time multi-camera video analytics system on GPU'' discusses a parallel implementation on a graphics processing unit (GPU) for intelligent video surveillance  ...  JRTIP is dedicated to the real-time aspects of image processing such as computational complexity reduction compared to existing solutions, real-time hardware implementation on various processors or platforms  ... 
doi:10.1007/s11554-016-0570-6 fatcat:vgxehq2nojau3l2k2coey7js5m

Design of Digital FIR Filter using Modified MAC Unit

M. Sathya
2018 International Journal for Research in Applied Science and Engineering Technology  
The output from the DSP processor is depends on the FIR filter, so need an efficient FIR filter design, to achieve an efficient output.  ...  To reduce the drawbacks, to propose a new efficient multiplier named as Birecoder multiplier. It is one of the best multiplier in the digital circuit design.  ...  sophisticated computer graphics and multi-media capabilities such as real time speech recognition and real time video.  ... 
doi:10.22214/ijraset.2018.1219 fatcat:elk7ymrzpnaotdtowvldc7vtkm

Table of contents

2004 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512) ISCAS-04  
IMAGE ENCODING METHOD FOR A REAL-TIME ...............  ...  Vaidyanathan, Bojan Vrcelj, California Institute of Technology, United States DSP-L12.5: IMPULSIVE NOISE REDUCTION IN DSL USING A NONLINEAR TEQ ... ....  ... 
doi:10.1109/iscas.2004.1328114 fatcat:xmvsmkhxgbb55ftuygqomthikm

VLSI Implementation of a High-Performance Nonlinear Image Scaling Algorithm

Osamah Ibrahim Khalaf, Carlos Andrés Tavera Romero, A. Azhagu Jaisudhan Pazhani, G. Vinuja, Ayush Dogra
2021 Journal of Healthcare Engineering  
This study implements the VLSI architecture for nonlinear-based picture scaling that is minimal in complexity and memory efficient.  ...  As a result, a low-cost VLSI architecture can be created. The results of simulations reveal that the effective weighted median interpolation outperforms other existing approaches.  ...  A real-time FPGA architecture of the extended linear convolution for the image scaling method [4] provides simple hardware architecture design with low computation cost.  ... 
doi:10.1155/2021/6297856 pmid:34336160 pmcid:PMC8321724 fatcat:n5pay6b3hfad5lnmha6urxa63e

design of image by morphological dilation technique.pdf

ganesh E N
Mathematical morphology is a well known image and signal processing technique. However, most morphological tools such Matlab are not suited for strong real-time constraints.  ...  The design is implemented on a Xilinx xc3s500e-4fg320 FPGA chip. The design is tailored to exploit certain features of sliding windows.  ...  Therefore, FPGAs are an ideal choice for implementation of real time image processing algorithms.  ... 
doi:10.6084/m9.figshare.19608105.v1 fatcat:bentrtzpx5h2vbitv6spzvcr3a

High-speed median filter designs using shiftable content-addressable memory

Chen-Yi Lee, Po-Wen Hsieh, Jer-Min Tsai
1994 IEEE transactions on circuits and systems for video technology (Print)  
This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many imagefvideo applications.  ...  The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells-sort-cell and compare-cell. Thus the design becomes very regular.  ...  ACKNOWLEDGMENT The authors would like to thank their colleagues within the VLSVCAD group of NCTU for many fruitful discussions.  ... 
doi:10.1109/76.340196 fatcat:4flca4z4ang5xpcr75isr6rpyq

A multichannel filter for TV signal processing

S. Vinayagamoorthy, K.N. Plataniotis, D. Androutsos, A.N. Venetsanopoulos
1996 IEEE transactions on consumer electronics  
Abstruct-A multichannel filtering approach is introduced here. The framework is used to correct impulsive noise and other image impairments in TV signal transmission.  ...  After that, a real-time digital signal processor board can be designed to implement the method.  ...  The new filter perfectly suitable for real time implementation was used to remove impulsive noise and other impairment from color TV signals.  ... 
doi:10.1109/30.494421 fatcat:5nlgay2fkrbszdr4p7nkwcrylq

Analysis of area-time efficiency for an integrated focal plane architecture

William H. Robinson, D. Scott Wills, Bhaskaran Vasudev, T. Russell Hsing, Andrew G. Tescher, Touradj Ebrahimi
2003 Image and Video Communications and Processing 2003  
For a Quad-CIF system resolution (176 x 144), results show that 1 PPE provides the optimal area-time efficiency (5.7 µs 2 • mm 2 for 250nm, 1.7 µs 2 • mm 2 for 120nm) but requires a large silicon chip  ...  Digitizing and processing a pixel at the detection site presents new design challenges, including the allocation of silicon resources.  ...  The total execution time for each PPE is within real-time constraints of 30 frames/sec (33.3ms per frame).  ... 
doi:10.1117/12.476615 fatcat:umwtzkkm2fc6fg3mpq7nv6hn5e

Fractal engine: an affine video processor core for multimedia applications

O. Fatemi, S.P. Panchanathan
1998 IEEE transactions on circuits and systems for video technology (Print)  
Fractal Engine An Affine Video Processor Core for Multimedia Applications Abstract The recent advances in VLSI technology, high-speed processor designs, Intemethtranet implementations, broadband networks  ...  We have chosen fractal block processing W P ) as a candidate algorithm for the design of target video processor, since it encompasses a variety of visual processing operations including affine transforrns  ...  For exarnple, the CLM4500 is a real time IIIIPEG-Z video encoder (for consumer quality), while the CLM4200 is a real time H.261 video codec-Both the CLM45ûû and CLM4200 processors are based on VideoRISC  ... 
doi:10.1109/76.735384 fatcat:sk2azaxd6je3nabiqjv5bfbrmy


M.Devipriya .
2014 International Journal of Research in Engineering and Technology  
The aim of this paper explores the power consumption technique for the architecture of Finite Impulse Response (FIR) adaptive filter.  ...  Thus a DA based implementation of adaptive filter is highly computational and area efficient.  ...  It is a powerful technique for reducing the size of a parallel hardware multiply-accumulate that is well suited to FPGA designs.  ... 
doi:10.15623/ijret.2014.0314001 fatcat:seac5jz2xfcuxgb62574qivzby

Real-Time Image and Video Processing: From Research to Reality

Nasser Kehtarnavaz, Mark Gamadia
2006 Synthesis Lectures on Image Video and Multimedia Processing  
After reading the book, the readers are exposed to a wide variety of techniques and tools, which they can then employ for designing a real-time image or video processing system of interest.  ...  KEYWORDS Real-time image and video processing, Real-time implementation strategies, Algorithmic simplifications for real-time image and video processing, Hardware platforms for real-time image and video  ...  A point was made that while VLSI, ASIC, or FPGAs can be used to meet the real-time constraint for video rate object detection, such solutions require a low-level hardware design that is often difficult  ... 
doi:10.2200/s00021ed1v01y200604ivm005 fatcat:aql6kiww3rhtje6py3uhw3p4f4

Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

Kumar Anubhav Tiwari, Armantas Ostreika, Jurate Platuziene
2017 Journal of Vibroengineering  
The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass,  ...  The core part of this paper was to find the reconfigurable and efficient architecture of the processor with only one multiplier which can work for Finite Impulse response (FIR) filter with the best-suited  ...  The FPGA-based architecture for 2-D FFTs was implemented for the real-time image filtering [23] .  ... 
doi:10.21595/jve.2017.18932 fatcat:jk5ubceoevgyfade65afeukvbq

On VLSI design of rank-order filtering using DCRAM architecture

Meng-Chun Lin, Lan-Rong Dung
2008 Integration  
This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for realtime speech and image processing applications.  ...  As shown in the result of physical implementation, the core size is 356.1 × 427.7μm 2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.  ...  For image processing, the performance of the proposed processor can process video clips of SVGA format in real-time. The rest of the paper is organized as follows.  ... 
doi:10.1016/j.vlsi.2007.05.002 pmid:19865599 pmcid:PMC2768317 fatcat:dftu6xtq75gxtmss7peox4l4ny
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